New in town: The Fetch Sequencer

7/23/2009

For the last few days I was having a really bad time trying to figure out the way of "decoding" an op. cod. fetch cycle. My original idea was to use the condition IR=0 (no op code) to trigger the OP COD FETCH sequence, but I'd always conceived this sequence being generated in the IDS card, hence the problem.

The thing is that reading the OP COD directly into IR (this takes place during T3) breaks the sequence right there, just when IR stops been zero. The obvious solution is not to read the op code directly into IR, but I cannot afford it because that is precisely the core of the Heritage/1 philosophy: to read things directly where they go in order to minimize data transfers... moreover, to eliminate intermediate data transfers at all.

Fortunately I found another solution. My original idea holds: The condition IR=0 triggers the OP COD FETCH sequence, but the circuit providing the sequence is not in the IDS card but in the MASTER CONTROLLER CARD. I called this circuit: "Fetch Sequencer" and it's relatively simple.

One curious detail about which I'm not entirely sure yet: This circuit will also generate the sequence for the Operand Fetch cycle. I mean, if the instruction requires operand fetching, the sequence will continue taking clock cycles T4, T5 and T6 to read the operand from memory into register OR. Then it will reset the T-COUNTER and deactivate the SF signal so IDS cards can take control... Is this... "natural"? Not sure, but I think it works... on paper at least.