CPU Backplane Pinout

- - - - - - - - - - - - - -    
     A        B       C
- - - - - - - - - - - - - -    
1    GND      GND     GND
2    D0       CTL     D8    
3    D1       CTL     D9
4    D2       CTL     D10
5    D3       CTL     D11
6    D4       CTL     D12
7    D5       CTL     D13
8    D6       CTL     D14
9    D7       CTL     D15
10   L0       L16     L8
11   L1       L17     L9
12   L2       L18     L10
13   L3       L19     L11
14   L4       L20     L12
15   L5       L21     L13
16   L6       CTL     L14
17   L7       CTL     L15
18   FLT      CTL     RST
19   CTL      CTL     CLK
20   SCSZ     CTL     SCS4
21   SCSN     CTL     SCS5
22   SCSC     CTL     SCS6
23   SCSV     CTL     SCS7
24   A7       CTL     A15
25   A6       CTL     A14
26   A5       CTL     A13
27   A4       CTL     A12
28   A3       CTL     A11
29   A2       CTL     A10
30   A1       CTL     A9
31   A0       CTL     A8
32   +5V      +5V     +5V
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Signals Descriptions:

DO-15       Internal Data Bus
A0-15       Internal Address Bus
L0-21       Internal Lamps Bus
SCSZ        Set Conditional Status Zero
SCSN        Set Conditional Status Negative
SCSC        Set Conditional Status Carry
SCSV        Set Conditional Status Overflow
SCS4        Set Conditional Status 4 (Future)
SCS5        Set Conditional Status 5 (Future)
SCS6        Set Conditional Status 6 (Future)
SCS7        Set Conditional Status 7 (Future)
RST         System Reset
CLK         System Clock
FLT         Fault Condition
CTL         Control Signals (Point-to-Point)

Except those marked as "PP" (Point to Poin), all signals in Control Slots are conneted into a Bus. Signals marked as CTL (Control) are not designated yet but they will as the design progresses.

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     A        B       C
- - - - - - - - - - - - - -    
1    GND      GND     GND
2    IR0      PP      IR8    
3    IR1      PP      IR9
4    IR2      PP      IR10
5    IR3      PP      IR11
6    IR4      PP      IR12
7    IR5      PP      IR13
8    IR6      PP      IR14
9    IR7      PP      IR15
10   CTL      CTL     CTL
11   CTL      CTL     CTL
12   CTL      CTL     CTL
13   CTL      CTL     CTL
14   CTL      CTL     CTL
15   CTL      CTL     CTL
16   CTL      CTL     CTL
17   CTL      CTL     CTL
18   FLT      CTL     RST
19   CCS      CTL     CLK
20   CSZ      CTL     CS4
21   CSN      CTL     CS5
22   CSC      CTL     CS6
23   CSV      CTL     CS7
24   CTL      CTL     CTL
25   CTL      CTL     CTL
26   CTL      CTL     CTL
27   CTL      CTL     CTL
28   CTL      CTL     CTL
29   CTL      CTL     CTL
30   CTL      CTL     CTL
31   CTL      CTL     CTL
32   CTL      CTL     CTL
33   CTL      CTL     CTL
34   CTL      CTL     CTL
35   CTL      CTL     S1
36   CTL      CTL     S0
37   CTL      CTL     EOE
38   CTL      CTL     ET1
39   CTL      CTL     ET0
40   +5V      +5V     +5V
- - - - - - - - - - - - - -    

Signals Descriptions:

IR0-15      Instruction Register Output
CCS         Clear Conditional Status
CSZ         Conditional Status Zero
CSN         Conditional Status Negative
CSC         Conditional Status Carry
CSV         Conditional Status Overflow
CS4         Conditional Status 4 (Future)
CS5         Conditional Status 5 (Future)
CS6         Conditional Status 6 (Future)
CS7         Conditional Status 7 (Future)
S0, S1      Operational Status
ET0, ET1    Enconded Time (T1, T2, T3, T4)
RST         System Reset
CLK         System Clock
FLT         Fault Condition
CTL         Control Signals (Bus)
PP          Control signals (Point-to-Point)


Encoded Time:

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ETT   ET0   Time
- - - - - - - - -
0    0     T1    
0    1     T2
1    0     T3
1    1     T4
- - - - - - - - -

Operational Status:

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S1   S0   Operational Status
- - - - - - - - - - - - - - - - - - - -
0    0    Halt
0    1    Fetch
1    0    Execute
1    1    Interrupt being negotiated
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