CLASSES #0, #1: Page Zero

    000 rr aaaaaaa ; register 'rr' <-- [ 00000 aaaaaaa ]  {  ldz r, addr }
    001 rr aaaaaaa ; register 'rr' --> [ 00000 aaaaaaa ]  {  stz r, addr }

    Direct addressing is limitted to registers A, B, C and D.
    In the mnemonic, addr represents the 7 least significant bits of the address
    being bits 8-11 all zeros.