IntroductionBranch Content
Computer Main Features
- 12-bits architecture clocked at 12 MHz.
- Console support for Single-Step execution, Halt-On-Fail and Halt-On-Break-Point
- One Accumulator (A), three aux registers (B, C, D) and one Index register (IX).
- ALU supports 2's complement and BCD arithmetic.
- Fast Ram (35ns) organized in 4K by 12-bit words.
- Memory space broken into 32 pages (128-words each) for direct addressing.
- Page-Zero direct addressing
- Indirect addressing via any of the registers: A,B,C,D,IX,PC,SP.
- Average instruction completes (fetch + exec) in 3 clock periods (250 ns), equivalent to 4 million instructions per second.
- Instruction decoding is made with hard-wired logic (no micro-programming)
- I/O accessible via 16 channels (no external bus)
- Memory expansion possible through RAM-DISK peripheral via I/O channel.
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