Control Signals in the U-BUSMDR: Memory Read
MWR: Memory Write
MWT: Wait (for synchronization with slow devices)
IRQ: Interrupt Request
IAK: Interrupt Acknowledge
BSY: Bus busy (not in 3rd. state)
SRT: System Reset
Note: Peripherals are memory mapped.
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Homebuilt CPUs WebRing
JavaScript by Qirien Dhaela
Join the ring?
David Brooks, the designer of the Simplex-III homebrew computer, has founded the Homebuilt CPUs Web Ring. To join, drop David a line, mentioning your page's URL. He will then add it to the list.
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Project start date: May 13 of 2009
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