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Overview

For all instructions in Heritage/1, the operational code takes a single 16-bits word. If an operand is needed, this is always the one 16-bit word following the Operational Code.

The Operational Code is divided into four 4-bits fields as shown below.

15                            0
[ CLASS ][ OTA  ][ OTD ][ LD  ]

The Instruction CLASS field (D12-15) determines how the other fields must be understood. It also determines whether the instruction requires an operand to be fetched and what actual circuit will decode the instruction.

For most instructions: OTA field (Output To Address) encodes the register providing the address, OTD (Output To Data) encodes the register used as source and LD field (Load) encodes the destination register. For memory read instructions, OTD = MRD (Memory Read signal); for memory write instructions, LD = MWR (Memory Write signal). Not used fields are filled with zeros.

Some instructions classes make special use of non-used fields as we shall see.

The following addressing modes have been implemented:

Register  : Data is contained in given register
            example: mov a, b      ; a=b

Immediate : Data if given in the word following the op. cod (operand).
            example: mvi  a, data  ;a=data

Direct    : Data is in the memory location which address is given in the word following the op. cod. (operand)
            example: ld a, addr    ; a=[addr]

Indirect  : Data is in the memory location which address is contained in a register used as a memory pointer
            example: ldx a, d      ; a=[d]

Relative  : (Branch only). Jump to OFF_SET relative to current instruction address. The OFF_SET if given as an operand.
            example: jnzr OFF_SET  ; pc=pc+OFF_SET

Relative Indirect: (Branch only). The OFF_SET is the content of given register.
           example: jnzrx  d      ; pc=pc+d

Stack     : Data comes from the Stack which is always pointed by register SP
            example:  pop a          ; sp=sp+1, a=[sp]

When a field represents a register, this is encoded according to the following table:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Value   Register         Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       PC               Program Counter
2       SP               Stack Pointer
3       OR               Operand Register
4       A                Accumulator
5       B                General Purpose reg
6       C                General Purpose reg
7       D                General Purpose reg
8       E                General Purpose reg
9-13   (reserved)        (Future use)
14      MRD              Memory Read signal              
15      MWR              Memory Write signal

For ALU instructions the OTA fields encode the ALU functions as following:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
OTA     Function       Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       ADD            Add
2       SUB            Subtract
3       CMP            Compare
4       AND            Logical AND  
5       OR             Logical OR
6       XOR            Logical XOR
7       SHFL           Shift Left
8       SHFR           Shift Right
9       SWP            Swap Nibbles
10-15   (Reserved)

Note:

All functions employ register A as left operand. The result is latched into A except for CMP which affects flags without altering A content.