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You are not implementing the so called MDR and MAR registers in this computer...

I am new to this matter and, yes, I've read about the so called MDR and MAR registers and I've seen how other homebrew designers have implemented such a thing, but -I may be wrong- I haven't seen the need for those so far in my design.

I read the instruction operational code from memory directly into the IR register (a single transfer: 2 clock periods) and it stays there for the instruction's life-term. Similarly, I read the operand (if any) into the Operand Register (OR) while my IR is still providing the operational code to the instruction decoding circuitry. I don't see the need for any intermediate register.

If the operand happens to be a direct address, I open the Address Buffer of the OR register for providing the address to the bus. If it happens to be an immediate value, I open the Data Buffer instead. It is maybe that I've replaced the so called MAR register with the double-buffering design of my registers... I don't really know, but again, I don't see the need for intermediate registers.

What I guess is that not having intermediate transfers will make my CPU to work faster... I guess...

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Project start date: May 13 of 2009