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Interrupter Device Requirements

Interrupter Devices must be designed to follow the above protocol. According the Heritage/1 design principles, LSI technology (such as programmable UART chips, PLAs etc) can NOT be employed to implement Device Controllers; the logic involved, however, is very simple.

The ISR address to provide is set with DIP switches standing behind a 3-state buffer (two 74HC244). The IAK signal does nothing but opening this buffer to the Data Bus.

The Daisy Chain is opened and closed with simple gates, thought the logic also involves a flip-flop to keep track of the "IRS running" state, which changes back upon ISE signal is received.

Other buffers and registers will surely needed for specific operations. The main idea is that the CPU will treat peripherals as memory locations and will access them "at memory speed". Delays associated with internal mechanisms (such as reading from magnetic tape to internal buffer) must take place when the peripheral is not being accessed, that is concurrently with normal CPU operations.