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Sequences

The previous example makes it clear the need for sequences. For example, to move  content from register B to register A, the following sequence is needed:

1.- Open register B to the D-BUS by activating the OTD_B signal.
2.- Load register A from the D-BUS by activating LD_A, while keep OTD_B active.
3.- Deactivate both OTD_B and LD_A.

Sequences are synchronous with the computer master clock (CLK). A central counter named T-COUNTER (clocked by the master clock) generates two "encoded-time" signals named ET0 and ET1 respectively. Sequences are actually built by combinatorial logic using ET0, ET1 as inputs.

The four possible combinations for ET0, ET1 are conventionally named: T1, T2, T3, T4 as following:

ET1   ET0   T
----------------
0     0     T1
0     1     T2
1     0     T3
1     1     T4
----------------

The time diagram below illustrates the execute cycle for the instruction:

        ldx  a, e

This instruction reads the memory location pointed by register E, into register A.


The time diagram shows the sequence of control signals OTA_E, MRD, LD_A needed to execute the given instruction. MRD (Memory Read) is an external signal present in the U-BUS wired to open the memory chip buffers to the Data Bus.

As shown, signals activate and deactivate at CLK period intervals as result of changes in ET0, ET1. The master clock (CLK) is currently 4 MHz thus this particular sequence takes 750 ns to complete. The shortest sequence in Heritage/1 takes one clock period (250 ns); the longest takes eight (2 us).

As mentioned, all sequences are built from ET0, ET1. The only exceptions are of those built by the Console; this exception has been made in order to minimize dependencies since the Console is meant to be the ultimate resource to control de computer in case of failure.