Instructions Set Architecture (ISA)

The architecture explained above yield to the following addressing modes.

    Mode                    Example             Descript
    --------------------------------------------------------------
    Register                ldr  A, B           r1:= r2

    Immeditate              ldi  A, value       r := value

    Direct                  ldd  A, address     r := [page + address]
                            sto  A, address     [page + address] := r

    Page-Zero Direct        ldz  A, address     r := [address]
                            stz  A, address     [address] := r

    Indirect                ldx  A, B           r1:= [r2]
                            stx  A, B           [r2]:= r1

    Indirect w/ auto-inc    ldy  A, B           r1:= [r2], r2++
                            sty  A, B           [r2]:= r1, r2++

    Index                   ldix A, d           r := [IX + d]
                            stix A, d           [IX + d] := r

    Stack                   push A              SP--, [SP]:=r
                            pop  A              r:=[SP], SP++
    ---------------------------------------------------------------

In Direct Addressing instructions, "address" is an 7-bits offset within the current memory page as explained in previous section.

Page Zero addressing allows direct access to memory locations in "page zero" (000H-07FF) independently from the page number currently held in S. This is an important feature because access to HER/12 memory is as fast as accessing registers, so Page Zero effectively provides 128 extra "registers" to the programmer.

Both Direct and Page Zero addressing are limited to registers A, B, C, PC.

Indirect Addressing is implemented by simply opening the desired pointer register to A-BUS.

Indirect with auto-increment is same as Indirect, only that the pointer register is post-incremented. This is convenient to software when looping through a memory buffer.

Indexed Addressing allows to point memory structure with IX, then get access to different fields within the structure by the mean of a 5-bits displacement (d).

The instruction's opcode and operands are encoded together in a single 12-bits word. The only exception is Immediate Addressing in which case the operand (value) is given in a second word following the opcode.

In the following sections, the notation r:= [ address ] means: copy the memory location which address is address, to register r. Expressions into curly braces represent mnemonics.

The three most significant bits of the opcode represents the "Instruction's Class", a code that selects the appropriate decoding circuitry. Remaining bits are encoded depending of the Class.

Classes are the following:

bin    dec    Descript                         Mnemonics
----------------------------------------------------------------------
000    0    Page Zero direct load              ldz
001    1    Page Zero direct store             stz
010    2    Direct addressing load             ldd
011    3    Direct addressing store            sto
100    4    Register or Immediate addressing   ldr, ldi
101    5    Indirect with or without auto-inc  ldx,stx,ldy,sty
110    6    Indexed (r <--> IX+d)              ldix,stix
111    7    Sub-Classe                         (all others)
----------------------------------------------------------------------

    000 rr aaaaaaa ; register 'rr' <-- [ 00000 aaaaaaa ]  {  ldz r, addr }
    001 rr aaaaaaa ; register 'rr' --> [ 00000 aaaaaaa ]  {  stz r, addr }

    Direct addressing is limitted to registers A, B, C and D.
    In the mnemonic, addr represents the 7 least significant bits of the address
    being bits 8-11 all zeros.

    010 rr aaaaaaa ; register 'rr' <-- [ ggggg aaaaaaa ]  {  ldd r, addr }
    011 rr aaaaaaa ; register 'rr' --> [ ggggg aaaaaaa ]  {  sto r, addr }

    
    Direct addressing is limitted to registers A, B, C and D.
    The 5-bits string 'ggggg' is the current page number held in register S.
    In the mnemonic, addr represents and offset of 7 bits withing the current page.

    100 rrr p00 sss        p=0 => rrr <-- sss   ; Register addressing     { ldr r1, r2   }
                           p=1 => rrr <-- value ; Immediate (sss ignored) { ldi r, value }

       In the case of Immediate addressing (p=1), the operand (value) is given
       in the word following the opcode.

Load/Store to register:

    101 rrr 0ip xxx        p=0 => rrr <-- [xxx] ; Load indirect   { ldx r, x }
                           p=1 => rrr --> [xxx] ; Store indirect  { stx r, x }
                           i=1    => Increment xxx after transfer { ldy r, x }{ sty r, x }

Read/Write to selected channel:

    101 000 10p xxx        p=0 => [xxx] <-- Channel Data path ; read data indirect  { ldch x }
                           p=1 => [xxx] --> Channel Data path ; write data indirect { stch x }
                          
    101 000 11p xxx        p=0 => [xxx] <-- Channel Control reg ; read ctl indirect  { ldct x }
                           p=1 => [xxx] --> Channel Control reg ; write ctl indirect { stct x }

These last four instructions provide the only way to access peripherals by software. Transfer is always indirect between Memory and the selected channel, using any of the suitable register as a pointer.

  110 rrr pdd ddd        p=0 => rrr <--[IX+ddddd] ; Load indexed  { ldix r, d }
                         p=1 => rrr -->[IX+ddddd] ; Store indexed { stix r, d }

Class 7 instructions constitute class extensions (or SubClasses). The subclass number is given in bits b6-8 of the opcode, being b9-11 = 111.

    111 ppp --- ---        ; ppp is the "sub-class" number

Depending of the SubClass, the instruction is encoded as following:

111 000 000 000      halt              Halt the computer
111 000 000 001      di                Disable interrupts
111 000 000 010      dt                Disable trap
111 000 000 011      ?
111 000 000 1..         ?

111 000 001 000      ?                  
111 000 001 001      ei                Enable Interrupts
111 000 001 010      et                Enable trap
111 000 001 011         ?

111 000 01. ...      ?
111 000 10. ...      ?
111 000 11. ...      ?

   111 001 0gg ggg    ; Set page ggggg       { setp page }
   111 001 10c ccc    ; Set channel cccc     { setch chn }

   111 010 rr ffff  
                          
   This instruction sets the ALU with the function 'ffff', then transfers register rr into A
   (if pertinent) to finally latch A with the result.

   Bits 'rr' are coded as following:

   rr  means:
   --------------------
   00  transfer from A
   01  transfer from B
   10  transfer from C
   11  ---lock ALU---
   --------------------

   The last (11) is a special case in which no result is obtained at that time. A second instruction
   is required to complete the operation. It works as following:

   If rr=11, 'ffff' is latched into register F, locking the ALU operation this way.

   The next instruction is expected to be a transfer to A. Since the ALU is locked with the
   function, the operation is effectively completed this time, obtaining the result in A.
   The ALU is automatically unlocked at the end of this second instruction.

   It follows from the above explanation that ALU instructions operates in two forms:
  
   DIRECT FORM (rr < 11):

      The operation is performed in that very instruction, but only registers A, B, C can be used
      as source for the operand.

      Example:

         ADD  B     ; A:=A+B


   DELAYED FORM (rr = 11):
      
      The operation is locked and completed in a second instruction that can be any having register
      A as destination. This allows to perform ALU operation using any addressing mode available to
      register A.

      Example:
  
         ADD  LOCK    ; Special assembly keyword 'LOCK' indicates DELAYED FORM
         LDD  A, addr ; A:=A+[addr]

      If the instruction following ADD LOCK is not a transfer to A, the operation is lost
      since 'ffff' is unlocked automatically at the end of the second instruction.

      This perhaps inconvenient implementation of ALU instructions can be camouflaged in Assembly
      language with pseudo-instructions. The Assembler would insert the second transfer instruction
      as appropriate.

      Examples of pseudo-instructions:

         ADDX B      ; A:=A + [B]
         ADDI value  ; A:=A + value


   ALU function (ffff) encodes as following


   ffff    Meaning
   -------------------------
   0000 => pass through
       ...
   (pending design)
       ...
   -------------------------

    111 011 pq1 ccc    ; Conditional jump, call or return
    111 011 pq0 000    ; Unconditional jump, call or return        

        p=0 => jump
        p=1 => call
        q=1 => return

        ccc (condition) can be:       mnemonic
        ---------------------------------------------------------------
        000  flag Z=1; zero           jz addr   { or cz, or  rz }
        001  flag C=1; carry          jc addr   { similar to above   }
        010  flag N=1; negative       jn addr   ...
        011  flag V=1; overflow       jv addr
        100  flag Z=0; non zero       jnz addr
        101  flag C=0; non carry      jnc addr
        110  flag N=0; positive       jnn addr
        111  flag V=0; no overflow    jnv addr
        ---------------------------------------------------------------

        Mnemonics for unconditional branching are:

        jp   addr
        call addr
        ret

        Call instructions save registers PC, F and S to the stack before branching.
        Return instructions pops registers S, F and PC from the stack before branching back.

    NOTE:

        Conditional branching is always immediate (address in second word operand).
        You can implement unconditional jump with other addressing modes by simply
        transferring an address to the PC, as in the following examples:

        ldr  PC, A    ; PC:=A, useful for computed branching.

        ldix PC, ptr  ; PC:=[IX + ptr ], say that 'ptr' is a pointer to function
                      ; stored as member of a structure being pointed by register IX.

    111 100 000 rrr    ; { push r }

       SP is decremented before transferring [SP]:=rrr

    111 100 100 rrr    ; { pop r }

       SP is incremented after transferring rrr:=[SP]

    111 101 00p rrr

        p=0 => register rrr is decremented  { dec r }  
        p=1 => register rrr is incremented  { inc r }

      111 11a aaa aaa

This instruction calls a subroutine which address is a pointer in Page Zero.

Example:

      callz 21; --> 111 110 010 001  (21 is Octal).

The content of memory cell at address 0021 is a pointer to the actual routine being called. Before passing control to the subroutine, the instruction pushes registers PC, F, S to the stack.

Notice that the first 16 addresses of Page Zero are meant to content pointers to hardware interrupts routines, following by a pointer to the Trap routine (address 20 octal). The instruction callz instruction is kind of "Software Interrupts". Address 21 (octal) is a good place for the first of such software interrupt routines.

Also notice that we can use callz to simulate a hardware interrupt by just calling an existing ISR.

Registers are encoded in instructions as following:

  000  A
  001  B
  010  C
  011  D
  100  IX
  101  SP
  110  PC
  111  K   Console Entry Switches (read-only).

==============================================================================================
    proj HERSIM -- ISA summary
==============================================================================================
Operational Code     Mnemonic          Description                                Cy   Flags
----------------------------------------------------------------------------------------------
000 rra aaa aaa      ldz r, addr       Load  page zero   r= [000 00a aaa aaa]     1    ZN
001 rra aaa aaa      stz r, addr       Store page zero   [000 00a aaa aaa]=r      1    ----
010 rra aaa aaa      ldd r, addr       Load  direct      r=[ppp ppa aaa aaa]      1    ZN
011 rra aaa aaa      sto r, addr       Store direct      [ppp ppa aaa aaa ]=r     1    ----
----------------------------------------------------------------------------------------------
100 rrr 000 sss      ldr r, s          Register  r=s
100 rrr 100 000      ldi r, value      Immediate r=[PC+1]

----------------------------------------------------------------------------------------------
101 rrr 000 xxx      ldx r, x          Load  indirect  r=[x]                      1    ZN
101 rrr 001 xxx      stx r, x          Store indirect  [x]=r                      1    ----
101 rrr 010 xxx      ldy r, x          with auto-inc   r=[x], x++                 1    ZN
101 rrr 011 xxx      sty r, x          with auto-inc   [x]=r, x++                 1    ----  

101 000 100 xxx      ldch x            Read channel indirect   [x]=channel        2    ----  
101 000 101 xxx      stch x            Write channel indirect  channel=[x]        2    ----
101 000 110 xxx      ldct x            Read channel control register indirect     2    ----
101 000 111 xxx      stct x            Write channel control register indirect    2    ----

----------------------------------------------------------------------------------------------
110 rrr 0dd ddd      ldix r, d         Load  indexed  r=[IX+d]
110 rrr 1dd ddd      stix r, d         Store indexed  [IX+d]=r

----------------------------------------------------------------------------------------------
111 000 000 000      halt              Halt the computer
111 000 000 001      di                Disable interrupts
111 000 000 010      dt                Disable trap
111 000 000 011      ?
111 000 000 1..         ?

111 000 001 000      ?                  
111 000 001 001      ei                Enable Interrupts
111 000 001 010      et                Enable trap
111 000 001 011         ?

111 000 01. ...      ?
111 000 10. ...      ?
111 000 11. ...      ?

----------------------------------------------------------------------------------------------
111 001 0gg ggg      setp  g           Set Page
111 001 10c ccc      setch c           Set Channel

----------------------------------------------------------------------------------------------
111 010 rrf fff      ALU      (--- pending design---)
111 010 11f fff      ALU LOCK (--- pending design---)

----------------------------------------------------------------------------------------------
111 011 000 000      jp   address      Unconditional jump
111 011 000 ...      ?

111 011 001 000      jz   address      Jump if Zero
111 011 001 001      jc   address      Jump if Carry
111 011 001 010      jn   address      Jump if Negative
111 011 001 011      jv   address      Jump if Overflow
111 011 001 100      jnz  address      Jump if Not Zero
111 011 001 101      jnc  address      Jump if Not Carry
111 011 001 110      jnn  address      Jump if Positive
111 011 001 111      jnv  address      Jump if Not Overflow

111 011 010 000      ret               Unconditional return
111 011 010 ...      ?

111 011 011 000      rz                Return if Zero
111 011 011 001      rc                Return if Carry
111 011 011 010      rn                Return if Negative
111 011 011 011      rv                Return if Overflow
111 011 011 100      rnz               Return if Not Zero
111 011 011 101      rnc               Return if Not Carry
111 011 011 110      rnn               Return if Positive
111 011 011 111      rnv               Return if Not Overflow
    
111 011 100 000      call address      Unconditional call
111 011 100 ...      ?

111 011 101 000      cz   address      Call if Zero
111 011 101 001      cc   address      Call if Carry
111 011 101 010      cn   address      Call if Negative
111 011 101 011      cv   address      Call if Overflow
111 011 101 100      cnz  address      Call if Not Zero
111 011 101 101      cnc  address      Call if Not Carry
111 011 101 110      cnn  address      Call if Positive
111 011 101 111      cnv  address      Call if Not Overflow

----------------------------------------------------------------------------------------------
111 100 000 rrr      push r            SP--, [SP]=r
111 100 100 rrr      pop  r            r=[SP], SP++

----------------------------------------------------------------------------------------------
111 101 000 rrr      dec r             r--
111 101 001 rrr      inc r             r++

----------------------------------------------------------------------------------------------
111 11a aaa aaa      callz addr           Call Page Zero