SubClass 010: ALU 111 010 rr ffff
This instruction sets the ALU with the function 'ffff', then transfers register rr into A
(if pertinent) to finally latch A with the result.
Bits 'rr' are coded as following:
rr means:
--------------------
00 transfer from A
01 transfer from B
10 transfer from C
11 ---lock ALU---
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The last (11) is a special case in which no result is obtained at that time. A second instruction
is required to complete the operation. It works as following:
If rr=11, 'ffff' is latched into register F, locking the ALU operation this way.
The next instruction is expected to be a transfer to A. Since the ALU is locked with the
function, the operation is effectively completed this time, obtaining the result in A.
The ALU is automatically unlocked at the end of this second instruction.
It follows from the above explanation that ALU instructions operates in two forms:
DIRECT FORM (rr < 11):
The operation is performed in that very instruction, but only registers A, B, C can be used
as source for the operand.
Example:
ADD B ; A:=A+B
DELAYED FORM (rr = 11):
The operation is locked and completed in a second instruction that can be any having register
A as destination. This allows to perform ALU operation using any addressing mode available to
register A.
Example:
ADD LOCK ; Special assembly keyword 'LOCK' indicates DELAYED FORM
LDD A, addr ; A:=A+[addr]
If the instruction following ADD LOCK is not a transfer to A, the operation is lost
since 'ffff' is unlocked automatically at the end of the second instruction.
This perhaps inconvenient implementation of ALU instructions can be camouflaged in Assembly
language with pseudo-instructions. The Assembler would insert the second transfer instruction
as appropriate.
Examples of pseudo-instructions:
ADDX B ; A:=A + [B]
ADDI value ; A:=A + value
ALU function (ffff) encodes as following
ffff Meaning
-------------------------
0000 => pass through
...
(pending design)
...
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