CLASS #7: Class Extensions (SubClasses)Class 7 instructions constitute class extensions (or SubClasses). The subclass number is given in bits b6-8 of the opcode, being b9-11 = 111.
111 ppp --- --- ; ppp is the "sub-class" number
Depending of the SubClass, the instruction is encoded as following:
SubClass 000: Control
111 000 000 000 halt Halt the computer
111 000 000 001 di Disable interrupts
111 000 000 010 dt Disable trap
111 000 000 011 ?
111 000 000 1.. ?
111 000 001 000 ?
111 000 001 001 ei Enable Interrupts
111 000 001 010 et Enable trap
111 000 001 011 ?
111 000 01. ... ?
111 000 10. ... ?
111 000 11. ... ?
subClass 001: Set Page or Channel
111 001 0gg ggg ; Set page ggggg { setp page }
111 001 10c ccc ; Set channel cccc { setch chn }
SubClass 010: ALU
111 010 rr ffff
This instruction sets the ALU with the function 'ffff', then transfers register rr into A
(if pertinent) to finally latch A with the result.
Bits 'rr' are coded as following:
rr means:
--------------------
00 transfer from A
01 transfer from B
10 transfer from C
11 ---lock ALU---
--------------------
The last (11) is a special case in which no result is obtained at that time. A second instruction
is required to complete the operation. It works as following:
If rr=11, 'ffff' is latched into register F, locking the ALU operation this way.
The next instruction is expected to be a transfer to A. Since the ALU is locked with the
function, the operation is effectively completed this time, obtaining the result in A.
The ALU is automatically unlocked at the end of this second instruction.
It follows from the above explanation that ALU instructions operates in two forms:
DIRECT FORM (rr < 11):
The operation is performed in that very instruction, but only registers A, B, C can be used
as source for the operand.
Example:
ADD B ; A:=A+B
DELAYED FORM (rr = 11):
The operation is locked and completed in a second instruction that can be any having register
A as destination. This allows to perform ALU operation using any addressing mode available to
register A.
Example:
ADD LOCK ; Special assembly keyword 'LOCK' indicates DELAYED FORM
LDD A, addr ; A:=A+[addr]
If the instruction following ADD LOCK is not a transfer to A, the operation is lost
since 'ffff' is unlocked automatically at the end of the second instruction.
This perhaps inconvenient implementation of ALU instructions can be camouflaged in Assembly
language with pseudo-instructions. The Assembler would insert the second transfer instruction
as appropriate.
Examples of pseudo-instructions:
ADDX B ; A:=A + [B]
ADDI value ; A:=A + value
ALU function (ffff) encodes as following
ffff Meaning
-------------------------
0000 => pass through
...
(pending design)
...
-------------------------
SubClass 011: Branching
111 011 pq1 ccc ; Conditional jump, call or return
111 011 pq0 000 ; Unconditional jump, call or return
p=0 => jump
p=1 => call
q=1 => return
ccc (condition) can be: mnemonic
---------------------------------------------------------------
000 flag Z=1; zero jz addr { or cz, or rz }
001 flag C=1; carry jc addr { similar to above }
010 flag N=1; negative jn addr ...
011 flag V=1; overflow jv addr
100 flag Z=0; non zero jnz addr
101 flag C=0; non carry jnc addr
110 flag N=0; positive jnn addr
111 flag V=0; no overflow jnv addr
---------------------------------------------------------------
Mnemonics for unconditional branching are:
jp addr
call addr
ret
Call instructions save registers PC, F and S to the stack before branching.
Return instructions pops registers S, F and PC from the stack before branching back.
NOTE:
Conditional branching is always immediate (address in second word operand).
You can implement unconditional jump with other addressing modes by simply
transferring an address to the PC, as in the following examples:
ldr PC, A ; PC:=A, useful for computed branching.
ldix PC, ptr ; PC:=[IX + ptr ], say that 'ptr' is a pointer to function
; stored as member of a structure being pointed by register IX.
SubClass 100: Stack
111 100 000 rrr ; { push r }
SP is decremented before transferring [SP]:=rrr
111 100 100 rrr ; { pop r }
SP is incremented after transferring rrr:=[SP]
Subclass 101: Increment / Decrement
111 101 00p rrr
p=0 => register rrr is decremented { dec r }
p=1 => register rrr is incremented { inc r }
SubClass 110, 111: Call Page Zero
111 11a aaa aaa
This instruction calls a subroutine which address is a pointer in Page Zero.
Example:
callz 21; --> 111 110 010 001 (21 is Octal).
The content of memory cell at address 0021 is a pointer to the actual routine being called. Before passing control to the subroutine, the instruction pushes registers PC, F, S to the stack.
Notice that the first 16 addresses of Page Zero are meant to content pointers to hardware interrupts routines, following by a pointer to the Trap routine (address 20 octal). The instruction callz instruction is kind of "Software Interrupts". Address 21 (octal) is a good place for the first of such software interrupt routines.
Also notice that we can use callz to simulate a hardware interrupt by just calling an existing ISR.
|