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EXT-BUS Gating

All EXT-BUS lines are behind 3rd state buffers in the MC unit. A "gating" logic is implemented in order to isolate external DMA transactions from Software running in MC private memory (internal buses) so they can take place concurrently. The logic is as following:

The bus is normally "closed" (high impedance state). In this conditions the Microprocessor access private memory and the Console register SAR (I/O address: 01 and 02). If the Microprocessor attempts to access external memory (address beyond 5FFFH) or I/O other than 01 and 02, the bus "opens", the signal BSY is activated in the bus to indicate that condition, and the lamp "BUS" is illuminated in the MC front panel.

A DMA capable peripheral requests bus control by raising the signal BRQ. In presence of this signal, the Bus Gating circuits closes the bus immediately (if it was not closed already). If the Microprocessor attempts to access external memory or I/O, a wait signal is asserted so the Microprocessor waits until the BRQ is dropped. The BSY signal however is not dropped. The operator can recognize this situation because lamps "BUS" and "WT" in the front panel are both illuminated.

Application programs are expected to run in Private Memory utilizing buffers located in External Memory shared with DMA peripherals. Access to those external buffers is negotiated with DMA as explained and the terms of the negotiation favors DMA in order to ensure the success of those (possibly critical) transactions.

DMA peripherals are expected to monitor the BSY signal, not to assert BRQ is it is active, and not to monopolize the bus for a long period of time.