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Console Electronics

The Console works independently (with no software support, except for the START operation), based in its own logic implemented with discrete TTL components. The circuit is broken into two boards: the Console Controller board and the Console Registers board. The later contains the console's registers, buffers and multiplexers as shown in the block diagram below. The former provides the necessary control signals sequences to manage those resources according to a logic triggered by the buttons and switches available to the operator in the front panel.


In the diagram, A-BUS and D-BUS represent the MC internal Address and Data bus respectively. All control signals (SW_LAR, LD_LAR etc.) are provided by the Console Controller board.

Register LAR (Lamps Address Register) holds the address being presented by the Address lamps. A 3rd-state buffer isolates this output from the A-BUS; control signal OTA_LAR (Output To Address) causes the buffer to open so the content is available in the A-BUS. The input may come from two different sources depending of the state of the preceding Multiplexor: that may be the Entry Switches or the A-BUS; signal SW_LAR determines the Multiplexor state: when active, the Multiplexor switches to A-BUS.

Signal LD_LAR (Load) makes the register to latch the input. Signal STEP_LAR causes the register to increment or decrement its content depending or DEC_LAR being inactive or active respectively.

Register LDR (Lamps Data Register) holds the content being presented by the Data lamps. The input may come from either the Entry Switches or the D-BUS. Buffered output goes to the D-BUS. Control signals SW_LDR, LD_LDR and OTD_LDR (Output to Data) have similar meanings as those in the LAR register. The LDR register, however cannot be incremented or decremented, only latched.

The register SAR (Start Address Register) holds the starting address for the program to be run when the operator presses the START button. Its 16 bits content is read by the Microprocessor into its PC register during a NMI interrupt asserted by the CPU board when the START button is pressed. This takes two reading operations: one for the LSB, other for the MSB, hence two buffers are necessary, triggered by control signals OTD_SAR_L and OTD_SAR_H respectively. These signals are generated by the Console Controller board when I/O ports 01H and 02H (respectively) are addressed by the Microprocessor.

When the operator presses the LOAD button, the status of the Entry Switches is latched in both registers LAR and SAR (signals LD_LAR, LD_SAR). The resulting memory address is read into LDR making the new content visible to the operator in the Data lamps.

When the operator presses the EXAMINE+ or EXAMINE- button, LAR is incremented (or decremented) and the resulting memory address is read into LDR.

Pressing the DEPOSIT button causes LDR to latch the Entry Switches state and that to be written into the memory location (or I/O device) addressed by LAR at that moment. LAR is automatically incremented and the resulting memory location (or I/O) is read again into LDR.

Control Signal sequences to allow all this to happen are built in the Console Controller board by the mean of a diodes matrix. Diodes are pluggable to allow further adjustments in the "microcode" if ever that would be needed.