InterruptsThe Heritage/1 interrupt architecture allows for 64K interrupts which priorities are determined by the hardware topology. Three control lines are present in the External Control Bus: IRQ (Interrupt Request), IAK (Interrupt Acknowledge) and ISE (Interrupt Services End). These lines are connected to all devices in a Daisy Chain fashion so any interrupter device can open the lines to avoid further propagation along the chain. This way, priority gets establiched by the "proximity" of the device to the CPU.
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Homebuilt CPUs WebRing
JavaScript by Qirien Dhaela
Join the ring?
David Brooks, the designer of the Simplex-III homebrew computer, has founded the Homebuilt CPUs Web Ring. To join, drop David a line, mentioning your page's URL. He will then add it to the list.
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Project start date: May 13 of 2009
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