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Status Bus (S-BUS)

SF   Fetch Cycle
SR   System Reset
S0   Operational Status
S1   Operational Status
CSZ  Conditional Status Zero
CSN  Conditional Status Negative
CSC  Conditional Status Carry
CS3  Conditional Status (Reserved)
CS4  Conditional Status (Reserved)
CS5  Conditional Status (Reserved)
CS6  Conditional Status (Reserved)
CS7  Conditional Status (Reserved)
CCS  Clear Conditonal Status
IE   Interrupt Enabled

SF signal is activated by instruction decoding logic (located at IDS cards) during the falling edge
of the last clock cycle of every instruction. The signal is used to syncrhonically clear both IR and the T-Counter; this action forces an Op Code Fetch Cycle taking place with the next clock rising edge.

S0, S1 define the current Operational Status according to the following table:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S1   S0   Operational Status
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0    0    Halt
0    1    Interrupt being negotiated (before ISR is called)
1    0    IDS having control in Step mode
1    1    IDS having control in Run  mode
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

If S1=0, IDS card ihibit themselves so other circuit (such as the Interrupt Controller or the Console) can take control of the machine. When S1=S0=1 and interrupt is enabled (IE=0), the Interrupt Controller card is allowed to serve interrupts. In that event, the Interrupt Controller will pull signal S1 down to zero for inhibiting IDS cards so it can take control of the machine while negotiating the interrupt with the interrupter device (see Interrupt life-time).

Conditional Status signals come from the Flags Registers (F). The first three are defined: CSZ, CSN, CSC; the other five (CS3-7) are reserved for future use. These signals are set from data oriented circuits; for instance, a register been cleared by an instruction will activate the CSZ signal). The signal CCS (activated by a controller such as an IDS card) will clear all flags at once.