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Principle of Operation

The circuit is actually a Finite State Machine (FSM) implemented with two D-type flip-flops (74ATC74) which outputs represent the status signals S0, S1. A simple combinational logic takes those, combined with others, and feeds the data (D) flip-flop's inputs with the "next status". The FSM changes status when the flip-flops are clocked by a "stimulus" signal provided by a logical OR of all possible "stimulus signals": /EOF, /EOE, /EOI, /START. (Note: In the diagram, the "logical OR" is actually a logical AND (U1) because input signals are active low).

The /START signal is a "pulse" provided by the Control Panel circuit. It occurs when the Operator pressed either HALT, RUN or STEP button on the Console.

The status output signals S0, S1 represent the current status of the computer, according to the following table.

S1  S0   Status
- - - - - - - - - - - - - - - - - - - - - - - - - -
0    0    Halt
0    1    Fetch Cycle
1    0    Execute Cycle
1    1    Interrupt being negotiated with peripheral
- - - - - - - - - - - - - - - - - - - - - - - - - -

Different circuits (such as the Fetch Sequencer, the IDS cards and the Interrupt Controller) use those as enable/disable signals. For instance, the Fetch Sequencer inhibit itself when S1,S0 is different from 0,1.

After reset, the Arbiter is in Halt status (S1,S0 = 00). When the operator pushes the RUN button on the Control Panel, the Halt flip-flop gets reset (/HLT=1) and the Arbiter changes status to S1,S0 = 01 to allow the Fetch Sequencer to start a new Fetch cycle.

Once the Fetch is completed, the Fetch Sequencer rises an "End of Fetch" (/EOF) signal which forces the Arbiter to change status to S1,S0 = 10; this authorizes IDS cards to start the Exec cycle.

When the Exec cycle finishes, the IDS card rises an "End of Execute" (/EOE) signal, signaling the Arbiter to change status again. The Arbiter decides what next according to the following logic:

If the Halt flip-flop is reset (/HTL=1) and there is not a pending interrupt request (/IRQ) from the Interrupt Controller, then:

- - - - - - - - - - - - - - - - -
Current   -->  Next  
- - - - - - - - - - - - - - - - -
0   0    -->  0 1      Go Fetch
0   1    -->  1 0      Go Exec
1   0    -->  0 1      Go Fetch
1   1    -->  0 1      Go Fetch
- - - - - - - - - - - - - - - - -

If the Halt flip-flop is set (/HLT=0), the output is forced to S1,S0 = 00.

If there is a pending IRQ, the output is forced to S1,S0 = 11 which authorizes the Interrupt Controller to start the Interrupt Sequence (negotiation with the interrupted device). When the sequence finishes, the Interrupt Controller drops the /IRQ signal and rises an "End of Interrupt" (/EOI) signal; in response, the Arbiter change status to 01 (Fetch).

Neither /IRQ nor /HLT signals will be sensed until the last execute cycle has finished, that is, when /EOE is active. This ensures that no instruction cycle will be left behind in the middle of the battle.

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Project start date: May 13 of 2009