Journal

This book contains "historical" information about the progress of the project. It is more personal than technical. Tech matters are placed in different Manuals. PreHistory Harry Porters Relay Computer So... I have to write a C compiler? Getting ready for Linux Project breakdown Unfinished Story Phase 1: Research Reading - Day One The Microprocessor temptation Wake up! Considering FPGA Simplified Memory Management and Protection Memory Allocation Scaling down System Calls The Matrix takes me to estrange roads The first Sketch for the CPU architecture Resizing the Matrix Writing the Spec Phase 2: Hardware Design Decision-Making and Testing Microcode or Hard-wired Logic? Considering PLDs The first step into reality Heritage/0 ? PREHER-816 Designing the PREHER-816 Quick Rearranging the web site for PREHER-816 Control Panel Lab Back to HERITAGE/1 BUS LAB Buying parts for the first time 16 Bits: A shine of elegance Buses, Cards and Backplane Approaching a final design of the Internal Bus Taking shape Opsss... Pins count exceeds the limit First Schematic finished First board being built New in town: The Fetch Sequencer Instruction Set Architecture Bus Controller and the new Backplane Parts are on their way Breadboard testing Fetch Sequencer Introducing the L-BUS Introducing the Arbiter Circuit Small Cards: a challenge Control Panel Layout Memory Bank register: defeated! The 64K words limit Rudimentary support for General Protection Conclusion Introducing Relative Branches Arbiter circuit tested Principle of Operation The Heritage/1 LAB implementation Wiring the Backplane What about "micro-dioded" logic? Entry Swithes: just another register Two boards for one Console Removing sixteen LEDs from the Console! Three registers will not fit in a single card Concern with the idea of having a "Control Bus" The fall of two milestones The Ruch for the Backplane Console boards being built Micro-dioded logic discarded Manuals Two months of inactivity Building the Console Controller Writting the Heritage/1 Assembler Reducing the Fetch cycle to 3 periods instead of 4 The Assembler is going well Direct and Indirect ALU operations Joined the David Brooks Homebuilt CPU Web Ring Leonel Norat joined the project! Hardware development on hold Reviewing the Instructions Set Architecture The new (revised) Instructions Set is complete Migrating to MS-DOS Working hard on the Simulator Finished ISA review Back to work From Heritage/1 to LC-81 The dificult decision was finaly made LC-81 to the rescue Ready to wire A final words

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