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Direct Branches (Class 2 branches)

Since "JP addr" is equivalent to: "MVI PC, addr", the unconditional jump instruction "JP addr" gets naturally encoded as a Class 2 instruction (Immediate transfers) as following:

[2][0][OR][PC], addr       0x2031  

For Conditional Branches, the condition is encoded in the OTA field as following:

[2][OTA][OR][PC], addr     Example: JNZ 0x03FF ; 0x2231, 0x03ff

OTA     Condition       Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       Zero            F0 = 1
2       Not Zero        F0 = 0
3       Negative        F1 = 1
4       Not Negative    F1 = 0
5       Carry           F2 = 1
6       Not Carry       F2 = 0
7       Overflow        F3 = 1
8       Not Overflow    F3 = 0
9       (Reserved)      F4 = 1
10      (Reserved)      F4 = 0
11      (Reserved)      F5 = 1
12      (Reserved)      F5 = 0
13      (Reserved)      F6 = 1
14      (Reserved)      F6 = 0
15      (Reserved)      F7 = 1

Note that the condition "OTA not equal to zero" could be confusing for the Class 2 decoding circuitry since it could either represents an immediate ALU instruction or a conditional branch. The circuit resolves the conflict by looking at the LD field: if LD=1 (PC) then it is a conditional branch instruction; otherwise it is an immediate ALU instruction.

Conditions 9-15 are "reserved" in the sense that no hardware circuit will set those flags for now. However, Class 2 instructions decoder circuitry is wired to cause actual jumps; for instance, the operational code "0x2a31, 0x3ff" will cause a jump to 0x3ff since F4 is zero after reset.