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Conditional Status and Flags Register

The Conditional Status describes the result of a data operation. This can be (not exclusive):

Zero     (Z): if the result is zero
Negative (N): if the result is negative
Carry    (C): Arithmetic carry
Overflow (V): if the result does not fit into the destination

Since the Conditional Status refers to a result and this is always kept in some register, detecting status is a job for the register's circuitry. Therefore, each register offers its own means for detecting its own Conditional Status.

The way for registers to deliver their individual status to the Flags register, is by the mean of a 4-bits bus (wired in the Data Slots) called S-BUS.

All registers are constantly generating status signals internally but, at a given time, only one is open to the S-BUS. This is because Flags should only be set according to the register being accessed by the current instruction and only if that instruction is meant to affect flags.

An exception to this rule are those instructions that increment or decrement two registers at the same time (INCM, DECM and INDEC). In this case both registers open to the S-BUS and flags are set as an "OR" of the individual conditions.

There are none dedicated control signals for opening registers to the S-BUS. The selection is made automatically when the register in question is Loaded, Incremented or Decremented.

Registers that are not meant to hold results, won't report conditional status (they are not wired to do so). Those are the following:

-- Program Counter (PC)
-- Stack Pointer (SP)
-- Operand Register (OR)
-- Instruction Register (IR)

The Flags register (F) resides in the Master Controller card (MC) which plugs to both Data and Control slots. The register is 8-bits but only 4 are used to remember the Conditional Status; a 5th. bit is used to remember the Interrupt Enabled condition as we shall see; the remaining 3 bits are implemented but not used (reserved for future use). The whole register F is saved to the Stack during CALL or Interrupt and restored back upon Return.

The register is actually made out of D-type flip-flops (74ACT74) fed from the S-BUS. The outputs go to another bus (called CS-BUS) wired in the Control Slots; this bus is always open so the current status is always available to Controller cards. Flags are latched selectively using signals LD_FZ, LD_FN, LD_FC and/or LD_FV produced by IDS cards during the last cycle of those instructions that affect flags.

Although further analysis on this topic is still pending , I can anticipate the following:

-- ALU instructions affect all flags (Z,N,C,V).
-- Data transfer instructions (MOV, LD, STO, PUSH, POP) affect flags Z, N.
-- Increment/Decrement instructions affect flags Z, N, V.
-- Branch instructions affect none flag.

By not affecting flags, I mean that the previous status remains. The programmer needs to take this into account when placing conditional branch instructions within the code.

The necessity of recording the Interrupt Enabled condition as a flag has to do with nested interrupts. When an interrupt service routine (lets call it: ISR1) gets interrupted by a highest priority interrupt (ISR2), the Interrupt Controller disables interrupts before passing control to ISR2. If this routine failed to enable interrupts back, then interrupts would remain disabled when control returns to ISR1, which is not the intended behavior. But, by remembering the Interrupt Enable condition in the Flags register, interrupts will be automatically restored upon return since F had been saved to the Stack.

Thus there is a flip-flop in F for the Interrupt Enable condition, only that its input (SI) and output (CSI) are not wired with the S-BUS and CS-BUS respectively but treated as point-to-point connections. This is because only a few circuits will make use of them; those circuits are: the Interrupt Controller, the IDS card responsible for the DI and EI instructions and the Control Panel.