Control SlotsExcept those marked as "PP" (Point to Poin), all signals in Control Slots are wired together in a Bus.
Signals marked as CTL (Control) are not designated yet but they will as the design progresses.
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A B C
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1 GND GND GND
2 IR0 PP IR8
3 IR1 PP IR9
4 IR2 PP IR10
5 IR3 PP IR11
6 IR4 PP IR12
7 IR5 PP IR13
8 IR6 PP IR14
9 IR7 PP IR15
10 CTL CTL CTL
11 CTL CTL CTL
12 CTL CTL CTL
13 CTL CTL CTL
14 CTL CTL CTL
15 CTL CTL CTL
16 CTL CTL CTL
17 CTL CTL CTL
18 RST CTL CTL
19 FLT CTL CTL
20 CSZ LD_FZ CTL
21 CSN LD_FN CTL
22 CSC LD_FC CTL
23 CSV LD_FV CLK
24 CTL CTL CTL
25 CTL CTL CTL
26 CTL CTL CTL
27 CTL CTL CTL
28 CTL CTL CTL
29 CTL CTL CTL
30 CTL CTL CTL
31 CTL CTL CTL
32 CTL CTL CTL
33 CTL CTL CTL
34 CTL CTL CTL
35 CTL CTL S1
36 CTL CTL S0
37 CTL CTL EOE
38 CTL CTL ET1
39 CTL CTL ET0
40 +5V +5V +5V
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Signals Descriptions:
IR0-15 Instruction Register Output
CSZ Conditional Status Zero
CSN Conditional Status Negative
CSC Conditional Status Carry
CSV Conditional Status Overflow
LD_FZ Load Flag Zero
LD_FN Load Flag Negative
LD_FC Load Flag Carry
LD_FV Load Flag Overflow
S0, S1 Operational Status
ET0, ET1 Enconded Time (T1, T2, T3, T4)
RST System Reset
CLK System Clock
FLT Fault Condition
CTL Control Signals (Bus)
PP Control signals (Point-to-Point)
Encoded Time:
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ET1 ET0 Time
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0 0 T1
0 1 T2
1 0 T3
1 1 T4
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Operational Status:
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S1 S0 Operational Status
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0 0 Halt
0 1 Fetch
1 0 Execute
1 1 Interrupt being negotiated
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Project start date: May 13 of 2009
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