CPU BACKPLANEThe CPU backplane is constructed on a prototyping board holding six 96-pins DIN41612 female connectors and other six 120-pins DIN41612 female connectors. This divides the backplane into two sections: Data Slots and Control Slots respectively. The former is used for "data oriented cards" (such as registers) and the latest is used for "controller cards".
Each of the two Slot types are wired separate. Most of the wires conforms different buses whereas others serve for point-to-point inter-card connections.
A special card named "Master Controller" features two connectors (one 96-pins and the other 120-pis) and plugs to both Slot types. This card contains those circuits that need access to the two worlds such as the Instruction Register (IR), the "Arbitrer" and others. It also provides the interface (buffering) with the external bus (U-BUS).
Following is the pinout for both Slot types:
Data Slots
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A B C
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1 GND GND GND
2 D0 PP D8
3 D1 PP D9
4 D2 PP D10
5 D3 PP D11
6 D4 PP D12
7 D5 PP D13
8 D6 PP D14
9 D7 PP D15
10 L0 PP L8
11 L1 PP L9
12 L2 PP L10
13 L3 PP L11
14 L4 PP L12
15 L5 PP L13
16 L6 PP L14
17 L7 PP L15
18 RST PP L16
19 FLT PP L17
20 SZ PP L18
21 SN PP L19
22 SC PP L20
23 SV PP CLK
24 A7 PP A15
25 A6 PP A14
26 A5 PP A13
27 A4 PP A12
28 A3 PP A11
29 A2 PP A10
30 A1 PP A9
31 A0 PP A8
32 +5V +5V +5V
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Signals Descriptions:
DO-15 Internal Data Bus
A0-15 Internal Address Bus
L0-20 Internal Lamps Bus
SZ Set Conditional Status Zero
SN Set Conditional Status Negative
SC Set Conditional Status Carry
SV Set Conditional Status Overflow
RST System Reset
CLK System Clock
FLT Fault Condition
PP Point-to-Point Control Signals
Control Slots
Except those marked as "PP" (Point to Poin), all signals in Control Slots are wired together in a Bus.
Signals marked as CTL (Control) are not designated yet but they will as the design progresses.
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A B C
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1 GND GND GND
2 IR0 PP IR8
3 IR1 PP IR9
4 IR2 PP IR10
5 IR3 PP IR11
6 IR4 PP IR12
7 IR5 PP IR13
8 IR6 PP IR14
9 IR7 PP IR15
10 CTL CTL CTL
11 CTL CTL CTL
12 CTL CTL CTL
13 CTL CTL CTL
14 CTL CTL CTL
15 CTL CTL CTL
16 CTL CTL CTL
17 CTL CTL CTL
18 RST CTL CTL
19 FLT CTL CTL
20 CSZ LD_FZ CTL
21 CSN LD_FN CTL
22 CSC LD_FC CTL
23 CSV LD_FV CLK
24 CTL CTL CTL
25 CTL CTL CTL
26 CTL CTL CTL
27 CTL CTL CTL
28 CTL CTL CTL
29 CTL CTL CTL
30 CTL CTL CTL
31 CTL CTL CTL
32 CTL CTL CTL
33 CTL CTL CTL
34 CTL CTL CTL
35 CTL CTL S1
36 CTL CTL S0
37 CTL CTL EOE
38 CTL CTL ET1
39 CTL CTL ET0
40 +5V +5V +5V
- - - - - - - - - - - - - -
Signals Descriptions:
IR0-15 Instruction Register Output
CSZ Conditional Status Zero
CSN Conditional Status Negative
CSC Conditional Status Carry
CSV Conditional Status Overflow
LD_FZ Load Flag Zero
LD_FN Load Flag Negative
LD_FC Load Flag Carry
LD_FV Load Flag Overflow
S0, S1 Operational Status
ET0, ET1 Enconded Time (T1, T2, T3, T4)
RST System Reset
CLK System Clock
FLT Fault Condition
CTL Control Signals (Bus)
PP Control signals (Point-to-Point)
Encoded Time:
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ET1 ET0 Time
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0 0 T1
0 1 T2
1 0 T3
1 1 T4
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Operational Status:
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S1 S0 Operational Status
- - - - - - - - - - - - - - - - - - - -
0 0 Halt
0 1 Fetch
1 0 Execute
1 1 Interrupt being negotiated
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