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Internal Buses

CPU internal buses are all wired in the Backplane. Those are the following:

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Name    Lines   Descript
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A-BUS   16      Address bus
D-BUS   16      Data bus
L-BUS   16      Lamps bus
S-BUS   4       Conditional Status source feding the flags register (F)
CS-BUS  4       Conditional Status: F unbuffered output to IDS cards
IR      16      Instructions Register unbuffered output to IDS cards

RST     1       Master Reset signal
CLK     1       Master clock (4MHz)
ET0,ET1 2       Sequence Encoded Time (T1,T2,T3,T4)
S0,S1   2       Machine Operational Status (Halt, Fetch, Exec, Interrupt)

C-BUS   80      Control Bus: All internal control signals wired as a bus
                for all IDS card slots (12-18)
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