Reviewing the Instructions Set Architecture06/20/2010
The current Instructions Set Architecture was designed nine months ago based on my early ideas about how instructions would be decoded using hardwired logic. I still think it's not a bad design, but it needs some adjustments and that's exactly what I am doing.
The new architecture relies, pretty much, on the same ideas, but it makes better use of bit-fields and it's better oriented to the decoding circuitry (yet to come). It is more rational, I think, and it also makes room for new instructions that I have in mind such as those for ALU operations with memory (not allowed by the current ISA) and increment/decrement instructions optimized for typical loops.
It is still pending how to produce long sequences such as the ones required for CALL and RET instructions (longer than 4 clock periods) but... I'm working on it.
|
Homebuilt CPUs WebRing
JavaScript by Qirien Dhaela
Join the ring?
David Brooks, the designer of the Simplex-III homebrew computer, has founded the Homebuilt CPUs Web Ring. To join, drop David a line, mentioning your page's URL. He will then add it to the list.
You will need to copy this code fragment into your page.
Project start date: May 13 of 2009
|
