Instruction ClassesHeritage/1 instructions are divided into "classes". The instruction class is the 4-bits number given by the most significant nibble of the operational code.
Class numbers are not arbitrary but closely related to the way instructions are decoded by the CPU circuitry. So far classes 1 to 11 have been defined; classes 12 to 14 are reserved for future use and class 15 represents a "class extension".
Class 15 instructions utilizes the next nibble (D9-12) to hold the "subclass". Remaining bits are conveniently encoded for the best use of decoding circuitry.
Following is a list of Heritage/1 Instruction Classes.
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HERITAGE/1 INSTRUCTION CLASSES AND SUBCLASSES
Note: Even classes and even subclasses require an Operand Fetch cycle
following the Operational Code Fetch Cycle.
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CLASS EXT OPND INSTRUCTIONS ADDRESSING MODE
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1 . mov r,s reg (ota=0 )
stox r,s indirect (ota<>0 )
jpx r jmp indirect unc. (ld=PC )
jprx r jmp relative indirect unc. (ld=1011)
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2 x mvi r, value inmediate
sto r, addr direct
jp addr jmp direct unc.
jpr offset jmp relative direct unc.
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3 . ldx r,s indirect
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4 x ld r, addr direct
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5 . add a, r ALU reg
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6 x adi a, value ALU inmmediate
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7 . addx a, r ALU indirect
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8 x addd a, addr ALU direct
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9 . inc r n/a
dec r
incm r,s
decm r,s
indec r,s
indec implicit
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10 x jnz addr jmp direct cond.
jnzr offset jmp relative direct cond.
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11 . jnzx r jmp indirect cond.
jnzrx r jmp relative indirect cond.
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CLASS EXTENSIONS
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15 1 . callx call indirect
callrx call relative indirect
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15 2 x call addr call direct
callr offset call relative direct
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15 3 . ret n/a
reti
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15 5 . int vector n/a
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15 7 . push r stack
pop r stack
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15 9 . hlt n/a
clrf n/a
di n/a
ei n/a
dt n/a
et n/a
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