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Fail Conditions

A number of fail conditions can be detected by the CPU circuitry causing the Fail Flip-Flop to set and the FAIL lamp to illuminate in the Console. Once set, condition can only be reset by pressing the button CLR in the Console.

Fail condition is sampled by the Arbiter at the end of the Exec cycle. If present, the ET counter is reset and state (S0,S1) is put to FETCH, or to HALT if the switch HOF (Halt On Fail) is ON.

If trap is enable (TE flip-flop set), a special interrupt (trap) is generated. However, this behavior is inhibited if the HOF switch is ON.

Following are the fail conditions recognized by the CPU:

An invalid instruction code is fetched and executed as normal, only that no sequencer will be able of generate control signals out of that code and, consequently, the End Of Sequence signal (EOS) will not be generated.

As a result, the ET count will continue to run until it exceed the permitted maximum value, which is 7. This count is produced by a 4-bits counter IC. In normal circumstances, it is reset earlier by the EOS signal but in this case, it will continue to run further.

As soon as the count gets to value 8 (more significant bit equals 1), the Fail condition is reported.

The WAIT signal present in each channel constitutes a potential problem. A defective peripheral could held that signal indefinitely causing the entire computer to freeze.

To prevent that, a time out of approximately 2 microseconds (32 clock periods) is put in place so if the WAIT signal is held by that long, the I/O operation is resumed and WAIT is ignored by other 2 microseconds.

When this anomaly occurs, a Fails condition is reported.