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Theory of Operation

The computer is, in general, a synchronous machine governed by internal control signals. These signals control the behavior of individual registers, buffers, multiplexers and other circuits, in a timely basis.

Below is a simplified block diagram of the CPU.




Registers and Memory communicate each other by the mean of an internal Data Bus (D-BUS), allowing transfer of data between then. The Console Entry Switches constitute a read-only register (K), also connected to the D-BUS.

The Address Bus (A-BUS) addresses the memory directly. Address is obtained from registers (indirect addressing) or directly from the instruction code (direct addressing).

The following diagram shows the interconnection of registers and memory to the buses with more details.


A third bus, namely Lamps Bus (L-BUS) inputs the Console Lamps Data Register (LDR) in the console to present different register's content in the Console DATA Display. Selecting a register for view in the Console actually means outputting that register (or Memory) to the L-BUS.

All these registers and related circuitry operate governed by internal control signals generated by different "Sequencer" circuits. These, in turn, operate in sync with "master control signals" generated by the Master Controller and distributed in the Control Bus (C-BUS).  

Sequencers and Master Control circuits are covered in details in section "Synchronization".

Most registers in the HER/12 are implemented using Synchronous Presetable up/down 12-bits counters (actually a combination of three 4-bits ICs). This implies the following:

  * Registers can be load in paralell from the D-BUS.
  * They can be incremented or decremented without ALU intervention.
  * Either load or inc/dec operations occurr in sync with the computer's master clock. That is,
    once the proper signals are applied (such as INC), the actual operation does not occur until
    the next falling edge of the clock in the middle of the period, takes place.



Counters outputs are isolated from the buses by the mean of 3-state buffers. These buffers are considered part of the register's circuit and they are the following:

  * Buffer to the A-BUS (internal address bus)
  * Buffer to the D-BUS (internal data bus)
  * Buffer to the L-BUS (internal lamps bus)

This last lead to the Console's LDR register to be shown in the DATA Display when the Operator selects that register in the Console.

Control signals related to registers are the following (using hypothetical register R):

   OTA_R      Output To Address: Open the buffer to A-BUS (indirect address)
   OTD_R      Output To Data: Open the buffer to D-BUS
   OTL_R      Output To Lamps: Open the buffer to L-BUS
   WR_R       Latch D-BUS content into register
   INC_R      Increment register content
   DEC_R      Decrement register content

OT? signals are asynchronous. WR, INC, DEC are synchronous and must be applied ahead of time (for example, at the beginning of the clock period) to be executed with the next falling edge of the clock master clock.

Operation WR_R takes priority over INC_R or DEC_R.

The flags register F is actually a set of individual flip-flops that can be set or cleared independently.

Flag are set or reset directly from registers A, B, C, D, IX, SP, at the time they are latched, incremented or decremented, according to the following logic:

After latched, incremented or decremented, if the content of the register resulted in zero, the Z flag is set, otherwise, Z is reset.

If bit 11 is one, then flag N is set. Otherwise, N is reset.

If an increment or decrement operation resulted in count roll-over (remember that registers are implemented with counter chips) then flag V is set. Otherwise, V is reset.

Flag C is set by the ALU when an arithmetic or logic operation results in an arithmetic or logical carry, reset otherwise.

Instructions that do not affect flags (for example, writing to memory), reset all four flags automatically. This is done by the Exec Sequencer circuit.

Instructions that test flags (for example, conditional jump) do reset all four flags after using them.

HER/12 memory is part of the CPU equipment and it is not extensible.

It is implemented using three SRAM chips, 4K by 4 bits each. Since the chips are directly addressable using the 12 bits available in the A-BUS, no decoding logic is needed: chips address pins are connected together and directly to the A-BUS. Same can be said about chips control pins CE (Chip Enable) and WE (Write Enable). Data pins are distributed among the 12 lines of the D-BUS.



The memory chips employed are very fast (35 ns). A half-clock period (42 ns) is long enough to have an stable data in the bus once the address and OE signals have been applied. Consequently, no synchronization logic is needed being the memory as fast as the CPU circuitry itself.

Control signals related to Memory are the following:

  * M     Connected to chips OE pins. Asserted for either reading or writing in Memory.
  * WR_M  Connected to chips WE pins. Asserted for writing in Memory.

The Memory Read Cycle takes one clock period.

Fist, the M signal is asserted. Also the address is put in the A-BUS at this time. As a result, the content of the addressed memory cell appears in the D-BUS.

Half clock cycle later (42 ns), this data is sufficiently stabilized in the bus. With the falling edge of the clock (in the middle of the cycle), the appropriated control signal WR_r is asserted to latch the data into the target register r.

At the end of the clock period, all signals are released.

The Memory Write Cycle takes one clock period.

All necessary signals are put in the buses at the begining of the clock period. These signals are: Address in the A-BUS, data in the D-BUS, M and M_WR.

Half clock later (42 ns), signals M and M_WR are pulled up. This makes effective the write operation into the memory chips.

At the end of the clock period, all signals are released.

Sequences of control signals are generated by four "sequencer" circuits. Those are:

  * Fetch Sequencer
  * Exec Sequencer
  * Interrupts Sequencer
  * Console Sequencer
    
These circuits are purely combinational, taking inputs from various "status signals" generated by a "Master Controller" circuit, and producing the different control signals at the outputs. The Instruction Sequencer in particular also takes input from register IR to produce sequences pertinent to the current opcode, effectively decoding the instruction.

All control signals are active low.

The Master Controller circuit contains the following elements:

  * Master Clock Oscillator
  * Encoded Time generator
  * Arbiter

The master clock (12 MHz) is generated by this circuit. This clock is the time-base for producing all other master and control signals, which in turn are the time-base for producing sequences of control signals.

Encoded Time signals ET0, ET1, ET2 represent an ascendant count (named "ET count") generated by a counter circuit clocked by the Master Clock. The count rolls over from 111 back to 000 if not terminated (reset) earlier.

Counts are conventionally named T1, T2,..., T8 as shown below:
    
   ET0  ET1   ET2     Name
   --------------------------------------
   0    0    0        T1
   0    0    1        T2
   0    1    0        T3
   0    1    1        T4
   1    0    0        T5
   1    0    1        T6
   1    1    0        T7
   1    1    1        T8
   --------------------------------------

These signals are inputs for the different sequencer circuits and serve to define sequence steps. Most sequences are short, taking only one or two steps. The longest are related to interrupts and CALL instructions and take eight steps to complete.

The machine is always in one and only one of the following states:

  * Halt
  * Interrupt
  * Fetch
  * Exec.

The Arbiter circuit dictates the computer's state by the mean of two master status signals (S0, S1), utilized to select the appropriate Sequencer, as shown in the table below. Only one sequencer is active at a given time.

   -------------------------------------------------------------------------------------------------
   S0   S1   State          Active Sequencer        Descript
   -------------------------------------------------------------------------------------------------
   0    0    Halt           Console Sequencer       Halted  
   0    1    Interrupt      Interrupt Sequencer     Taking care of interrupt before calling the ISR
   1    0    Fetch          Fetch Sequencer         Instruction Fetch cycle
   1    1    Exec           Exec Sequencer          Instruction Exec cycle
   -------------------------------------------------------------------------------------------------

In terms of implementation, S0 and S1 are distributed in a bus (C-BUS, for "Control Bus") along with other signals to reach the different sequencers. Each sequencer is wired to inhibit itself unless S0,S1 have the appropriate value. Also wired in that bus is a signal named EOS (End Of Sequence), imputing the Arbiter. Sequencers pull this signal down when the sequence they produced comes to an end.

The Arbiter circuit generates the master status signals S0, S1 according to the following logic.

After reset, S1,S0 = 0,0 (Halt), and remains in that state until the button RUN is pressed in the Console.

Pressing the button RUN causes the Arbiter to reset the ET count and set S1,S0 = 1,0 (Fetch). Consequently, the next clock period becomes the time T1 for the Fetch Sequencer which generates a Fetch sequence. With the falling edge of the clock in the middle of the last cycle, signal EOS is pulled down by the Fetch Sequencer to notify it has finished.

In reaction to the EOS signal, the Arbiter resets the ET count and puts S1,S0 = 1,1 (Exec). Consequently, the next clock period becomes the time T1 for the Exec Sequencer, which starts the corresponding sequence.

The exec cycle can take from 1 to 8 clock periods depending of the instruction. When finished, the Arbiter is notified via EOS signal.

In response, the Arbiter resets the ET count and checks if there is an Interrupt request. If that is the case and interrupts are enabled, the Arbiter puts S1,S0 = 0,1 (Interrupt), otherwise S1,S0 = 1,0 (Fetch).

In case of interrupt, the Interrupt Sequencer generates a sequence to push registers PC, F, S to the stack, then to load PC with the ISR address. After that, the Interrupt Sequencer sends the EOS signal in response to which the Arbiter resets the ET count and put S1,S0 = 0,1 (Fetch) effectively starting the ISR routine.

Notice that the Fetch, Exec and Interrupt sequencers run one sequence at the time and then return control to the Arbiter. The case of the Console sequencer is different in this respect, since it can run an undefined number of sequences at the Operator's request without returning to the Arbiter. This is a potential problem which solution is this: the Console Sequencer does not take ET0, ET1, ET0 signals as inputs; it generate the different sequence steps using internal timing. It follows that the Console Sequencer is not a pure combinational circuit as other sequencers are.

The Instruction Fetch Cycle is generated by the Fetch Sequencer when status signals S1,S0 equals: 1,0.

The sequence takes one clock period, being a memory read cycle (as explained earlier) using register PC as the address provider and IR as the destination register.

The Program Counter register (PC) is incremented during T1 of the Exec cycle overlapping this operation with others pertinent to the current instruction's Exec cycle.

The Instruction Exec Cycle is generated by the Exec Sequencer when status signals S1,S0 = 11.

The Instruction Sequencer has IR for input, so sequences are assembled depending of the current OpCode, effectively decoding and executing the current instruction.

We will not cover all instruction sequences in here; suffice is to say that they can vary taking between 1 and 8 clock periods to complete, depending of the instruction.

The first period (T1) is always used to increment the Program Counter (PC), in addition to produce the control signals pertinent to the instruction per se. To do this, signal INC_PC is activated at the beginning of T1 and will remain activate all T1 long; consequently, PC will be effectively incremented with the falling edge of the clock in the middle of T1. This must not cause any problem as long as the instruction in course is not working with PC. If it is (for example, a branch instruction) then WR_PC will compete with INC_PC at half T1. The dispute is resolved in favor of WR_PC thanks to proper design of the PC register circuitry.
    
The case of instructions with Immediate Addressing is special because the operand is in the memory word pointed by an incremented PC. In this case, period T1 is dedicated to just increment PC; control signals to perform the actual transfer will appear at T2. The next period (T3) is used to increment PC further so it points to the next instruction in memory.

Notice that the instruction LDI PC value will result in PC=value+1, because, as mentioned, PC is incremented at T3 of the exec cycle.

When the Instruction Exec sequence finishes, all signals are released and signal EOS to the Arbiter which, in response, will set to put S1,S0 = 1,1 so a new Fetch cycle can start at the next clock period.

To illustrate how sequences are built in HER/12 sequencer circuits, we will consider the execution of a simple instruction:

    LDR A, B

    which causes the content of register B to be copied into register A.

The instruction's exec cycle completes in one clock period (T1), as illustrated in the time diagram below.


First, both OTD_B, WR_A control signals appear simultaneously, causing the content of B to be put in the D_BUS. Register A, however, won't latch until the next falling edge of the clock. This is due to register's design as we discussed previously. With that falling edge we also fire the End Of Sequence signal (EOS).

The instruction is encoded in a generic way valid for all registers, as discussed in section "Instruction Set Architecture (ISA)". If bits 11,10,9 (instruction class) are "100" and bits 5,4,3 are "000", then the following circuit will generate the intended sequence; otherwise, none of the output control signals will be activated.


Fist of all, S0,S1 must be "11". Notice in the diagram that all decoders will be inhibited otherwise causing all control signals at the output to be 1 (inactive).

Secondly, the "instruction class" must be "100"; otherwise decoders U3, U4 will be inhibited producing no signal at the output (all ones).

Third, the control signals appear at T1, that is, when E0,E1,E2 = "000".

Finally, bits 5,4,3 must be "000", and this is specific to this instruction in particular.

Decoders U3, U4 decode the appropriate source and target registers directly from the instruction's code. In this case, OTD_B and WR_A would be produced.

The "End of Sequence" (EOS) signal is generated synchronous with the clock by U5..

In fact, this circuit is part of a bigger one. Other sequencer circuits similar to this would be connected to the others U1's outputs, one for each instruction class. Those circuits would take signals T1, T2,... etc, from U2, as appropriate.

This circuit is only an example. Possibly it deserves better design, but it illustrates the following general rules:

  * Instruction sequencer circuits inhibit them self is S1,S0 is different from "11" (exec state).
  * Different instruction classes select different sequencer circuits.
  * The ET count (E0,E1,E2) define different steps within the sequence.
  * Fields encoded in the instruction (such as registers) are decoded directly by sequencer's circuitry.

A number of fail conditions can be detected by the CPU circuitry causing the Fail Flip-Flop to set and the FAIL lamp to illuminate in the Console. Once set, condition can only be reset by pressing the button CLR in the Console.

Fail condition is sampled by the Arbiter at the end of the Exec cycle. If present, the ET counter is reset and state (S0,S1) is put to FETCH, or to HALT if the switch HOF (Halt On Fail) is ON.

If trap is enable (TE flip-flop set), a special interrupt (trap) is generated. However, this behavior is inhibited if the HOF switch is ON.

Following are the fail conditions recognized by the CPU:

An invalid instruction code is fetched and executed as normal, only that no sequencer will be able of generate control signals out of that code and, consequently, the End Of Sequence signal (EOS) will not be generated.

As a result, the ET count will continue to run until it exceed the permitted maximum value, which is 7. This count is produced by a 4-bits counter IC. In normal circumstances, it is reset earlier by the EOS signal but in this case, it will continue to run further.

As soon as the count gets to value 8 (more significant bit equals 1), the Fail condition is reported.

The WAIT signal present in each channel constitutes a potential problem. A defective peripheral could held that signal indefinitely causing the entire computer to freeze.

To prevent that, a time out of approximately 2 microseconds (32 clock periods) is put in place so if the WAIT signal is held by that long, the I/O operation is resumed and WAIT is ignored by other 2 microseconds.

When this anomaly occurs, a Fails condition is reported.

Fail Trap is a special interrupt generated by the CPU when a Fail Condition is detected.

This interrupt is disabled after reset and, if wanted, it needs to be enabled by software (TE flip-flop set). In addition, the Enable Trap switch (TRAP) in the Console must be ON and the Halt-On-Fail switch (HOF) must be OFF.

A pointer to the trap routine is in memory at address 010H. When called, the fail flip-flop is reset automatically.