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Channel Signals

The following signals are available to the peripheral in the channel.


   Signal     In or Out  Descript
   -----------------------------------------------------------------------
  
    OL          I        Device Online
    D0-11       I/O      Data from/to either CONTROL or DATA register.
    SEL         O        Select device register (0:DATA, 1:CONTROL).
    RD          O        CPU reads from selected device register.
    WR          O        CPU writes to selected device register.
    INT         I        Device requires attention.
    ACK         O        CPU acknowleges the interrupt.
    WAIT        I        Hold the RD/WR cycle.
    RST         O        Reset signal

The OL bit indeicates whether the device is "Online". This condition is stablished manualy by the operator of the device. The CPU refrains from accessing the device when the OL bit is clear.

Data path is 12 bits though some peripherals (example, a terminal) may use a shorter path in which case it must pad unused bits with zeros.

SEL is normally 0 to select the peripheral's data path (DATA register); it becomes 1 to select the peripheral's CONTROL register instead.

RD and WR are used to synchronize data exchange. When reading, the CPU pulls RD down to request data; in response, the peripheral must output the 12-bits data word in D0-11. When writing, the CPU writes the data in D0-11, then pulls WR down; in response, the peripheral must read D0-11 into its
internal DATA register.

INT is held down by the peripheral to request CPU attention. This line must be held until line ACK becomes active.

ACK is activated (down) by the CPU to acknowledge the interrupt. In response, the peripheral must release INT and get ready for data transfer. Most likely the CPU will perform a read operation on the CONTROL register to learn the nature of the request.

Some devices might be fast enough so not to require interrupt synchronization but slow, still, compared to the CPU speed; in those cases, the WAIT signal is used. When WAIT is down, the read or write cycle freezes waiting for the peripheral to complete its part. The peripheral must activate this signal as soon as the RD or WR signal is detected, hold it for as long as required, then release it to finish the operation. In response to WAIT release, the CPU completes its part: either latching the read data or disconnecting the channel from the D-BUS.

The WAIT signal can not be monopolized indefinitely which would cause the entire machine to freeze because of a defective peripheral. A time out of 32 clock cycles (2 micro seconds aprox) prevents this from happening. If the WAIT signal is held by that long, the I/O operation resumes and the WAIT signal is ignored by other 32 clock cycles. An alarm condition is raised to notify the anomaly.

RST is the master reset signal affecting the CPU and all devices. It is opt to the device to pay attention to this signal.

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