Table of Content  Branch Up  

I/O Architecture

Every peripherals connects to the CPU by the mean of a circuit called "Channel". The term has been borrowed from early IBM main frames, only that those were based on smaller dedicated computers (such as IBM 1401) whereas HER/12 channels solely provides a connection between the peripheral and the CPU buses, with no intelligence at all.

Up to 16 channels are supported but only one can connect to the CPU buses at a given time; that is said to be the "selected" channel. Selection can be made by software during normal program execution or manually by the mean of the Console when the computer is halted.

Data transfer is always between the selected channel and memory, using indirect addressing. The channel never reads or writes directly to a register.

Communication with peripherals is always initiated from the CPU. Peripherals can, at the most, assert interrupt signals to get CPU attention.

    The device is expected to have at least two 12-bits internal registers:
    DATA and CONTROL.

    DATA holds the data to be transferred in one direction or the other;
    CONTROL reports status and accepts commands. A bit (SEL) supplied
    in the channels determines whether the dialog is from/to the DATA or
    the CONTROL register.

    The word length can be less than 12; for example, a Terminal device
    will possibly have only 8 bits data path. In those cases, the device
    must accommodate the used bits in the least significant portion of
    the word, padding the rest with zeros.

    Devices can also have other registers, but those would not be addressable
    by the channel. Some sort of addressing via the CONTROL register would
    be required in such cases.

    The device accepts signals RD, WR to synchronize data transfer. It also
    asserts an interrupt signal (INT) when it feels appropriate and accepts
    an acknowledge signal (ACK) from the channel.

    Devices can also synchronize by using a WAIT signal. When active, the
    CPU delays the read or write cycle waiting from the device to complete
    its part.

The following signals are available to the peripheral in the channel.


   Signal     In or Out  Descript
   -----------------------------------------------------------------------
  
    OL          I        Device Online
    D0-11       I/O      Data from/to either CONTROL or DATA register.
    SEL         O        Select device register (0:DATA, 1:CONTROL).
    RD          O        CPU reads from selected device register.
    WR          O        CPU writes to selected device register.
    INT         I        Device requires attention.
    ACK         O        CPU acknowleges the interrupt.
    WAIT        I        Hold the RD/WR cycle.
    RST         O        Reset signal

The OL bit indeicates whether the device is "Online". This condition is stablished manualy by the operator of the device. The CPU refrains from accessing the device when the OL bit is clear.

Data path is 12 bits though some peripherals (example, a terminal) may use a shorter path in which case it must pad unused bits with zeros.

SEL is normally 0 to select the peripheral's data path (DATA register); it becomes 1 to select the peripheral's CONTROL register instead.

RD and WR are used to synchronize data exchange. When reading, the CPU pulls RD down to request data; in response, the peripheral must output the 12-bits data word in D0-11. When writing, the CPU writes the data in D0-11, then pulls WR down; in response, the peripheral must read D0-11 into its
internal DATA register.

INT is held down by the peripheral to request CPU attention. This line must be held until line ACK becomes active.

ACK is activated (down) by the CPU to acknowledge the interrupt. In response, the peripheral must release INT and get ready for data transfer. Most likely the CPU will perform a read operation on the CONTROL register to learn the nature of the request.

Some devices might be fast enough so not to require interrupt synchronization but slow, still, compared to the CPU speed; in those cases, the WAIT signal is used. When WAIT is down, the read or write cycle freezes waiting for the peripheral to complete its part. The peripheral must activate this signal as soon as the RD or WR signal is detected, hold it for as long as required, then release it to finish the operation. In response to WAIT release, the CPU completes its part: either latching the read data or disconnecting the channel from the D-BUS.

The WAIT signal can not be monopolized indefinitely which would cause the entire machine to freeze because of a defective peripheral. A time out of 32 clock cycles (2 micro seconds aprox) prevents this from happening. If the WAIT signal is held by that long, the I/O operation resumes and the WAIT signal is ignored by other 32 clock cycles. An alarm condition is raised to notify the anomaly.

RST is the master reset signal affecting the CPU and all devices. It is opt to the device to pay attention to this signal.

    A device interrupts the CPU using the interrupt line (INT) located in
    the channel it is connected to.

    All INT signals coming from all channels go to the Interrupt Controller
    circuit. A priority encoder provides a 4-bits code of the interrupting
    device (matching its channel number) and takes care of priorities in case
    of simultaneous request: channels with smaller numbers take priority.

    The interrupt signal is sampled at the end of each instruction cycle,
    just before fetching next instruction's op-code. If active, the interrupt
    is serviced instead  of performing the op-code fetch.
    
    Servicing the interrupt implies the following:

    Registers PC, F and S are pushed to the stack, channel switched to that of
    the interrupting device, and the appropriate interrupt service routine (ISR)
    is called. The sixteen 12-bit addresses of those routines are expected to be
    at the top of the memory space:

        000: ISR0_ADDR
        001: ISR1_ADDR
        ...
        00F: ISR15_ADDR

    That address is loaded into the Program Counter (PC), the ACK signal is
    asserted in the interrupting channel and interrupts are automatically
    disabled to avoid unwanted nested interrupts.

    The next opcode fetch cycle takes place on the corresponding ISR.

    The ISR finishes with a return instruction. That instruction automatica-
    lly pops S, F and PC from the stack, returning control to the interrupted
    program. IRS routines are expected to enable interrupts back before
    returning.

Inter-devices communication is possible, it can be implemented in the device per se, but the CPU brings no support for that.

Implementing inter-device communication between a tape drive controller and a RAM-DISK device, for example, could provide some sort of Direct Memory Access (DMA), but, again, that would be in the rein of device's design, the CPU provides nothing to support such a thing.