Interrupts A device interrupts the CPU using the interrupt line (INT) located in
the channel it is connected to.
All INT signals coming from all channels go to the Interrupt Controller
circuit. A priority encoder provides a 4-bits code of the interrupting
device (matching its channel number) and takes care of priorities in case
of simultaneous request: channels with smaller numbers take priority.
The interrupt signal is sampled at the end of each instruction cycle,
just before fetching next instruction's op-code. If active, the interrupt
is serviced instead of performing the op-code fetch.
Servicing the interrupt implies the following:
Registers PC, F and S are pushed to the stack, channel switched to that of
the interrupting device, and the appropriate interrupt service routine (ISR)
is called. The sixteen 12-bit addresses of those routines are expected to be
at the top of the memory space:
000: ISR0_ADDR
001: ISR1_ADDR
...
00F: ISR15_ADDR
That address is loaded into the Program Counter (PC), the ACK signal is
asserted in the interrupting channel and interrupts are automatically
disabled to avoid unwanted nested interrupts.
The next opcode fetch cycle takes place on the corresponding ISR.
The ISR finishes with a return instruction. That instruction automatica-
lly pops S, F and PC from the stack, returning control to the interrupted
program. IRS routines are expected to enable interrupts back before
returning.
|
