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Master Controller

The Master Controller circuit contains the following elements:

  * Master Clock Oscillator
  * Encoded Time generator
  * Arbiter

Master Clock oscilator

The master clock (12 MHz) is generated by this circuit. This clock is the time-base for producing all other master and control signals, which in turn are the time-base for producing sequences of control signals.

Encoded Time signals (ET0, ET1, ET2)

Encoded Time signals ET0, ET1, ET2 represent an ascendant count (named "ET count") generated by a counter circuit clocked by the Master Clock. The count rolls over from 111 back to 000 if not terminated (reset) earlier.

Counts are conventionally named T1, T2,..., T8 as shown below:
    
   ET0  ET1   ET2     Name
   --------------------------------------
   0    0    0        T1
   0    0    1        T2
   0    1    0        T3
   0    1    1        T4
   1    0    0        T5
   1    0    1        T6
   1    1    0        T7
   1    1    1        T8
   --------------------------------------

These signals are inputs for the different sequencer circuits and serve to define sequence steps. Most sequences are short, taking only one or two steps. The longest are related to interrupts and CALL instructions and take eight steps to complete.

Arbiter and Master Status signals (S0, S1)

The machine is always in one and only one of the following states:

  * Halt
  * Interrupt
  * Fetch
  * Exec.

The Arbiter circuit dictates the computer's state by the mean of two master status signals (S0, S1), utilized to select the appropriate Sequencer, as shown in the table below. Only one sequencer is active at a given time.

   -------------------------------------------------------------------------------------------------
   S0   S1   State          Active Sequencer        Descript
   -------------------------------------------------------------------------------------------------
   0    0    Halt           Console Sequencer       Halted  
   0    1    Interrupt      Interrupt Sequencer     Taking care of interrupt before calling the ISR
   1    0    Fetch          Fetch Sequencer         Instruction Fetch cycle
   1    1    Exec           Exec Sequencer          Instruction Exec cycle
   -------------------------------------------------------------------------------------------------

In terms of implementation, S0 and S1 are distributed in a bus (C-BUS, for "Control Bus") along with other signals to reach the different sequencers. Each sequencer is wired to inhibit itself unless S0,S1 have the appropriate value. Also wired in that bus is a signal named EOS (End Of Sequence), imputing the Arbiter. Sequencers pull this signal down when the sequence they produced comes to an end.

The Arbiter circuit generates the master status signals S0, S1 according to the following logic.

After reset, S1,S0 = 0,0 (Halt), and remains in that state until the button RUN is pressed in the Console.

Pressing the button RUN causes the Arbiter to reset the ET count and set S1,S0 = 1,0 (Fetch). Consequently, the next clock period becomes the time T1 for the Fetch Sequencer which generates a Fetch sequence. With the falling edge of the clock in the middle of the last cycle, signal EOS is pulled down by the Fetch Sequencer to notify it has finished.

In reaction to the EOS signal, the Arbiter resets the ET count and puts S1,S0 = 1,1 (Exec). Consequently, the next clock period becomes the time T1 for the Exec Sequencer, which starts the corresponding sequence.

The exec cycle can take from 1 to 8 clock periods depending of the instruction. When finished, the Arbiter is notified via EOS signal.

In response, the Arbiter resets the ET count and checks if there is an Interrupt request. If that is the case and interrupts are enabled, the Arbiter puts S1,S0 = 0,1 (Interrupt), otherwise S1,S0 = 1,0 (Fetch).

In case of interrupt, the Interrupt Sequencer generates a sequence to push registers PC, F, S to the stack, then to load PC with the ISR address. After that, the Interrupt Sequencer sends the EOS signal in response to which the Arbiter resets the ET count and put S1,S0 = 0,1 (Fetch) effectively starting the ISR routine.

Notice that the Fetch, Exec and Interrupt sequencers run one sequence at the time and then return control to the Arbiter. The case of the Console sequencer is different in this respect, since it can run an undefined number of sequences at the Operator's request without returning to the Arbiter. This is a potential problem which solution is this: the Console Sequencer does not take ET0, ET1, ET0 signals as inputs; it generate the different sequence steps using internal timing. It follows that the Console Sequencer is not a pure combinational circuit as other sequencers are.

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