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Memory Read Cylcle

The Memory Read Cycle takes one clock period.

Fist, the M signal is asserted. Also the address is put in the A-BUS at this time. As a result, the content of the addressed memory cell appears in the D-BUS.

Half clock cycle later (42 ns), this data is sufficiently stabilized in the bus. With the falling edge of the clock (in the middle of the cycle), the appropriated control signal WR_r is asserted to latch the data into the target register r.

At the end of the clock period, all signals are released.

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