Memory Write CycleThe Memory Write Cycle takes one clock period.
All necessary signals are put in the buses at the begining of the clock period. These signals are: Address in the A-BUS, data in the D-BUS, M and M_WR.
Half clock later (42 ns), signals M and M_WR are pulled up. This makes effective the write operation into the memory chips.
At the end of the clock period, all signals are released.
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