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Instruction Fetch Cycle

The Instruction Fetch Cycle is generated by the Fetch Sequencer when status signals S1,S0 equals: 1,0.

The sequence takes one clock period, being a memory read cycle (as explained earlier) using register PC as the address provider and IR as the destination register.

The Program Counter register (PC) is incremented during T1 of the Exec cycle overlapping this operation with others pertinent to the current instruction's Exec cycle.