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Instruction Exec Cycle

The Instruction Exec Cycle is generated by the Exec Sequencer when status signals S1,S0 = 11.

The Instruction Sequencer has IR for input, so sequences are assembled depending of the current OpCode, effectively decoding and executing the current instruction.

We will not cover all instruction sequences in here; suffice is to say that they can vary taking between 1 and 8 clock periods to complete, depending of the instruction.

The first period (T1) is always used to increment the Program Counter (PC), in addition to produce the control signals pertinent to the instruction per se. To do this, signal INC_PC is activated at the beginning of T1 and will remain activate all T1 long; consequently, PC will be effectively incremented with the falling edge of the clock in the middle of T1. This must not cause any problem as long as the instruction in course is not working with PC. If it is (for example, a branch instruction) then WR_PC will compete with INC_PC at half T1. The dispute is resolved in favor of WR_PC thanks to proper design of the PC register circuitry.
    
The case of instructions with Immediate Addressing is special because the operand is in the memory word pointed by an incremented PC. In this case, period T1 is dedicated to just increment PC; control signals to perform the actual transfer will appear at T2. The next period (T3) is used to increment PC further so it points to the next instruction in memory.

Notice that the instruction LDI PC value will result in PC=value+1, because, as mentioned, PC is incremented at T3 of the exec cycle.

When the Instruction Exec sequence finishes, all signals are released and signal EOS to the Arbiter which, in response, will set to put S1,S0 = 1,1 so a new Fetch cycle can start at the next clock period.