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The Computer

Computer Name       : PREHER/816
Data Bus            : 8 bits
Address Bus         : 24 bits external (16 bits internal)
Main Memory         : Up to 16 MB SRAM distributed in 256 banks 64 KB each.
Arithmetic          : Signed integer (two's complement)
Inst. decode method : Hard-wired logic

Real-Time Timer     : Computer "tic". Interrupts the CPU at 1ms intervals
Peripherals         : Memory Mapped
Interrupts          : (Decision pending)
DMA                 : (Decision pending)

Technology          : SSI/MSI HCMOS chips (Considering: PLD)
Construction        : Prototyping boards housed in home-made multi-card frames.
Clock Speed         : (Decision pending; expected: 12 MHz)

The PREHER/816 minicomputer consists of several cabinets called "units" joined together by a common bus called U-BUS. Units are home-made multi-cards frames. The U-BUS, though composed by data, address and control lines, looks like a single multi-wire cable ending in DSUB connectors.

Units can be combined in flexible ways to make different configurations. The most basic configuration consists of one CPU unit. Practical configurations will include the STORAGE unit (Hard drives) and the COMM unit (RS3232 and Ethernet). More units can be developed as needed.

The CPU Unit (a home-made multi-cards frame) has two buses in the backplane: the A-BUS (16 address lines) and the D-BUS (8 data lines). Different cards connect to those buses. Other connections such as internal control signals also exists between cards. The U-BUS is the external bus; only the "Bus Controller Card" is connected to it. The U-BUS is not present in the backplane.

The CPU architecture is pretty classical. The register A (accumulator) serves as left operand and result for the ALU. It is not possible to obtain ALU results in a register other than A. What it is possible, however, is to transfer data between 8-bits and 16-bits registers using instructions such as: "movh b, y".

The register MB (Memory Bank) provides support for a memory banking scheme allowing for 16 MB of memory divided in 256 banks of 64KB each. Note that the internal address bus (A-BUS) is 16 bits so the banking scheme is optional and has no impact to the rest of the architecture.

There is not MDR/MAR registers but a 16-bits MDAR register which sole mission is to hold the operand for immediate and direct addressing modes instructions. The Instruction Decoder and Sequencer (IDS) is hard-wired (no micro coded) implemented with PLD chips.

8-bits registers (Data oriented):

A    Accumulator (Right operand and result for ALU operations)
B    General purpose
C    General purpose
D    General purpose
E    General purpose

16-bits Registers (Address oriented):

PC   Program Counter
SP   Stack Pointer (also a gernal purpose 16-bits register)
X    Pointer for Indirect Address (also a gernal purpose 16-bits register)
Y    Pointer for Indirect Address (also a gernal purpose 16-bits register)

Hidden Registers:

IR    (8 bits) Instruction register
MDAR  (16 bits) Operand holder (both 8 and 16 bits)
FLAGS (?)       Status flags

-Register  : Data is conteined in given register
 Examples  : mov a, b    ; A <- B
           : movh a, sp  ; A <- SP (MSB)

-Immediate : Data if given in the byte(s) following the op. cod.
 Examples  : movi  a, data  ; A <- 8-bits data
           : movi sp, data  ; SP <- 16-bits data

-Direct    : Data is in the memory location which address is given in the two bytes following the op. cod.
 Example   : ld a, addr    ; A <- [addr]

-Indirect  : Data is in the memory location which address is contained in register X or Y
 Example   : ldx a, x      ; A <- [X]

-Stack     : Data comes from the Stack (always pointed by register SP)
 Example   : pop a          ; A <- [SP]; SP <- SP-1

-INC/DEC   : Register is incremented or decremented in a sigle clock cyle (no data transfer occurs).
 Example   : dec c          ; C <- C-1