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16 Bits: A shine of elegance

06/30/2009

I seemed happy enough with my 8-bit design when suddenly, at mid night, a totally different design came to my mind and I had no option but to jump to my acrylic white board and start sketching the new idea. I don't want to post anything yet other than this little note, until the idea is more mature.

The new architecture for the Heritage/1 is 16-bits both address and data. This means that all registers are 16 bits and implies that any of them can be used as a pointer. This simple fact completely defeats the notion of "data-oriented" and "address-oriented" registers.

Indeed this is nothing new. The PDP-11 was just like that and same approach has been followed by homebrew CPU designers like John Doran.

As per my Heritage/1, I have the following plan:

Except for special registers such as IR (Instruction Register) and MDAR (Operand holder), all regs will be built using counters (74HC169). This allows the CPU  to execute INC/DEC instructions in just one clock cycle since no ALU operation nor data transfer is involved.

Not only counters, of course, but 3-state buffers (74HC244) too. Actually, each reg will have two buffers: One to the internal D-BUS (Data Bus) and the other to the external Address Bus. This way each reg can write to either bus. Inputs, however, always come from the D-BUS.

The other change has to do with the instruction decoding mechanism. I'm still determined to use hardwired logic instead of micro-coding (that is for the sake of speed and also because I find it more interesting); however, now that I have a 16-bits instruction (instead of 8) I have room for field-mapping.

This is the idea:

No matter what the data transfer, there are always two registers involved: a source (SRC) and a destination (DES). If data is transferring between registers, that is pretty clear; if it is from or to memory, one register is receiving or sending the data while the other is supplying the address (Ex: PC, SP or any reg used as pointer in a indirect addressing instruction).

So for any data-transfer instruction I only need two fields to say what registers are involved: SRC and DES. For the current design, 3 bits each would be enough, but I will make them 4-bits so I have room for 8 more registers in the future.

After had expending 8 bits in field-mapping, I yet have 8 bits for instruction OP-COD so I can build up to 256 instruction which is more than enough.

And having this reg addresses coded within the instruction I can simplify the logic by using 4-to-16 decoder chips. I will use three of them: One for "data-read" (open buffer to D-BUS) control signals, one for  "data-write" (clock registers) control signals, and the other for "address-open" (open buffer to the Address Bus) control lines.

That is basically the idea for the new architecture. I think is elegant and promising. And I hope not to come with a new redesign before this project evolve in a total mess.

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Project start date: May 13 of 2009