Table of Content  Branch Up  

Interrupts Architecture

The Heritage/1 CPU can accept up to 64K non-vectored hardware interrupts while only three control lines are employed for negotiation. Nested interrupt service routines (ISR) are possible according to priorities.

The CPU also accepts 256 vectored software interrupts which vectors are shared with interrupts generated by the CPU itself such as Fault and Timer.

There are two moments in the life of an interrupt: Negotiation and Service. During the first, the CPU and the interrupter device negotiate the use of the buses until finally the ISR address is passed from the device to the CPU. The second moment starts when the CPU passes control to the ISR (PC loaded with the ISR address) and finishes when the ISR returns and control is passed back to the interrupted routine.

During interrupt negotiation, the Interrupt Controller takes over; this is coordinated by mean of status signals S0, S1 present in the Status Bus (S-BUS).

Once the ISR address has been obtained, the Interrupt Controller saves the Program Counter (PC) and Flags register (F) to the stack. Finally it loads the PC with the ISR address and rises an End Of Interrupt (EOI) signal so the next Op Fetch cycle can take place over the interrupt service routine.

Interrupter Peripherals don't provide "vectors" but instead the actual address of the Interrupt Service Routine (ISR). Therefor, up to 64K different external interrupts are possible.

External interrupts can be enabled (EI) and disabled (DI) by software. When the interrupt occurs, the CPU disables interrupts automatically. Every ISR is expected to enable interrupts back to allow for nested interrupts service.

Three control lines are present in the External Control Bus for serving external interrupts: IRQ (Interrupt Request), IAK (Interrupt Acknowledge) and ISE (Interrupt Service End). These lines connect to all devices in Daisy Chain so any interrupter device can open the lines to avoid further propagation along the chain. This way, priority gets established by the "proximity" of the device to the CPU.

Here is the sequence of events during an interrupt.

0.- Initially, no interrupt is being requested. IRQ, IAK and ISE lines are inactive and the buses are being used by the CPU to run the current routine.

1.- Some DEVICE wants to interrupt. The first thing it does is to open the chain to avoid IRQ and IAK signals to propagate further along the chain. Then, it signals the CPU for attention by activating the IRQ line.

2.- The CPU finishes the current instruction, then disables interrupts (DI) and signals the DEVICE to provide the interrupt address by activating the IAK signal. The device is expected to release the address immediately (within a clock cycle); IAK is actually a "read" signal similar to "Memory Read" (MRD).

3.- The DEVICE provides the interrupt address which is read into the the Operand Register (OR) during the next clock cycle. The CPU deactivates IAK to notify the DEVICE.

4.- When the DEVICE notices that IAK is not longer present, it releases the Bus and drops the IRQ signal.

5.- The CPU can now utilize the buses so it saves PC and F to the Stack, then transfer OR to PC for passing control to the interrupt service routine (ISR). This routine is expected to enable interrupts back (EI).

6.- When the Interrupt Service Routine reaches the RETI instruction (return from interrupt), the CPU recovers F and PC from the stack for passing control back to the previous routine. Then, it rises the signal ISE (Interrupt Service End).

7.- Until this moment, the DEVICE had kept the chain open so less priority devices could not interrupt. Now, it utilizes the ISE signal to close the chain back. If a less priority device had issue an interrupt request already, it will now reach the CPU for attention.

NOTE: The ISE signal is a low-going pulse, half-a-clock wide. The interrupter device is expected to close the chain with the rise edge of the puse so the pulse itseft don't propagate further.

If you "run" this sequence with multiple devices interrupting at the same time, you will see how different ISRs nest each another observing the priorities set by device proximity.

Interrupter Devices must be designed to follow the above protocol. According the Heritage/1 design principles, LSI technology (such as programmable UART chips, PLAs etc) can NOT be employed to implement Device Controllers; the logic involved, however, is very simple.

The ISR address to provide is set with DIP switches standing behind a 3-state buffer (two 74HC244). The IAK signal does nothing but opening this buffer to the Data Bus.

The Daisy Chain is opened and closed with simple gates, thought the logic also involves a flip-flop to keep track of the "IRS running" state, which changes back upon ISE signal is received.

Other buffers and registers will surely needed for specific operations. The main idea is that the CPU will treat peripherals as memory locations and will access them "at memory speed". Delays associated with internal mechanisms (such as reading from magnetic tape to internal buffer) must take place when the peripheral is not being accessed, that is concurrently with normal CPU operations.

Internal interrupts can be generated by Software, from the Timer or when a Fault condition is detected. All internal interrupts are vectored (8-bits vector).

Vectors occupy all together the first 256-words block of the addressable space: 0x0000-0x00ff. Vector 0 is at 0x0000, vector 1 is at 0x0001 and so on. Each location contains the actual address of the corresponding Interrupt Service Routine.

Certain circuits in the CPU are capable of detecting fault conditions such as illegal instruction. When a Fault is detected, the Interrupt Controller is notified. It reacts by taking control of the CPU for saving PC and F to the stack, then loading the Program Counter (PC) with the content of memory location 0x0001. This behavior, however, can be changed from the computer Console so the computer simply halts on Fault.

This interrupt is not affected by the DI instruction.

The Timer is located in the Interrupt Controller. It is a simple counter triggered from the System Clock and wired to produce interrupts at long intervals (for example, 1 ms) set by DIP switches.

The address for the Timer Service routine is indicated in memory location 0x0000. When the timer interrupts, the Interrupt Controller loads the Program Counter (PC) with the content of that memory location (after have saved PC and F to the Stack).

This interrupt is not affected by the DI instruction but it can be disabled from the Console.

The instruction INT generates a Software Interrupt. This instructions takes one argument (embedded within the operational code) which is the 8-bits interrupt vector.

Notice that address 0x0000 is the one for the Timer and 0x0001 is the one for Fault. This means that both Timer and Fault interrupts can be simulated by software (INT 0 and INT 1 respectively).

Priorities are in this order:

1.- Timer
2.- Fault
3.- External
4.- Software