Table of Content  Branch Up  

Instruction Set Architecture

7/25/2009

Today is Saturday and I went no where. Instead, I spend all day defining the final Instruction Set Architecture up to the ultimate details.

I came with the concept of "Instruction Classes" to group instructions that are similar in implementation so I can reuse decoder circuitry. I also defined all instructions in my Set and all ALU operations (they are not too many).

Curiously, the design taken me to unexpected results such as the "multiple" INC/DEC instructions (Ex: INCM E, D) which "naturally" increment two registers simultaneously in a single clock cycle. This is the kind of surprise that I really enjoy.

Honesly, it has been hard for me to get to this point. Decoding instructions with hardwired logic resulted more difficult than expected, specially since that logic must be distributed among several cards. The Heritage/1 experience has been unique in that regard: the first circuits drafted were unacceptably complex but they were gradually gained in simplicity up to what they are now: unbelievable simple circuits.

The core of Heritage/1 design is still simplicity, which ironically contradicts the very nature of a (complex) project of this kind.