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Introducing the Arbiter Circuit

08/23/2009

Until now, control coordination between the Fetch Sequencer, the IDS cards and the Interrupt Controller relied on four "status signals" (SH, SF, SE, SI: Status Halt, Fetch, Execute and Interrupt respectively).

Problems arose when I started to sketch the actual circuits. These signals came from different places to fight each others under inhibit/enable rules. At the implementation level, that proven to be a mess.

I came today with a different, much more decent approach. Now the status is coded in two signals named: S0 and S1, according with the following table:

S1   S0   Status
- - - - - - - - - - - - - - - - - - - - - -
0     0   Halt
0     1   Fetch (either code or operand)
1     0   Execute
1     1   Interrupt being negotiated

These signals comes from a new circuit called ARBITRER. IDS cards and the Interrupt Controller listen to them and keep themselves inhibited until the appropriate status arrives.

When execution finishes, the IDS generate an "End Of Execution" (EOE) signal back to the ARBITER which in turn generates the appropriate signals to either halt the computer (case of STEP execution) or clear the IR to enforce the new Fetch cycle. Similarly, the Interrupt Controller rises an "End of Interrupt" (EOI) when negotiation with peripheral is over.

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