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Reducing the Fetch cycle to 3 periods instead of 4

6/1/2010

Tonight, an old premise (held since July 2009) fall, resulting in a 25% increase of the average performance... according to raw calculations.

It was established since before that the Op. Code Fetch cycle should take 4 clock periods:

T1    Open PC to the A-BUS (OTA_PC)
T2    Memory Read signal   (MRD)
T3    Read the bus into IR (LD_IR)
T4    Increment PC         (INC_PC)

Since every instructions requires an Op. Code Fetch cycle, this T4 doing nothing else apart for incrementing the PC represented a serious waste of overall execution time. Here is how I took it away.

Following the Op. Code Fetch cycle is either the Operand Fetch cycle or the first period (T1) of the exec cycle.

I realized that PC is never used in execution during T1. Even branch instructions (the only ones that get to write into PC) don't touch that register until T2, so we are really plenty of time during T1 for activating the INC_PC signal in order to increment PC at that time. This will reduce the Op. Code Fetch cycle (as well as the Operand Fetch cycle) to 3 periods instead of 4.

So now we have:

---- Op. Code Fetch ---------------
T1    Open PC to the A-BUS (OTA_PC)
T2    Memory Read signal   (MRD)
T3    Read the bus into IR (LD_IR)
--- Exec --------------------------
T1    Increment PC (INC_PC)... apart from whatever the instruction needs to do.
T2    ... the instruction continues to execute.

Doing the same for Operand Fetch cycle is also possible. PC was opened to the A-BUS during Op. Code Fetch and now it needs to remain open during Operand Fetch while it's being incremented (at T1); however the Memory Read signal (MRD) will not come until T2 (250 ns later) which is long enough for the data to stabilize in the bus... (I hope).

An additional advantage is that now the INC_PC signal can be obtained very easily. In fact, INC_PC must appear always at the same time: T1 of either Operand Fetch or Execution cycles.

The machine "knows" that she is in Exec cycle because S0=1 and S1=0. It also knows of T1 because ET0=ET1=0. Decoding such condition will be enough for obtaining the INC_PC signal. The Fetch Sequencer circuits will need to help, however, by providing INC_PC during T1 of the Operand Fetch cycle but that is easy too.

Finally, I did some calculations with my Instructions Set (adjusted for the new durations) which revealed an average of 6.18 cycles per instruction, that is 1.5 microseconds assuming a clock of 4 MHz. Before if was 2 microseconds... not too bad.

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