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Instruction Classes

As mentioned before, the Instruction CLASS determines how the other fields must be understood. It also determines whether the instruction requires an operand to be fetched and what actual circuit will decode the instruction.

Instructions classes are the following:

- - - - - - - - - - - - - - - - - - - - - -
Class  Description        Clock Cycles
- - - - - - - - - - - - - - - - - - - - - -
0      Null Class                  -
1      Register                    2
2      Immediate                   2
3      Direct                      3
4      Indirect                    3
5      Relative Direct             3
6      Relative Indirect           3
7      Stack Push                  4
8      Stack Pop                   4
9      Inc/Dec                     1
10     Call Direct                (more than 4)
11     Call Relative              (more than 4)
12     Call Relative Indirect     (more than 4)
13-14  (Future)                    -
15     Class Extensions            -

[1][0][r2][r1]        Example: MOV  A, B  ; 0x1045
[1][f][r ][A]                  ADD  A, B  ; 0x1145

[2][0][OR][r], value       Example:  MVI A, 0xffff  ; 0x2034, 0xffff
[2][f][OR][A], value                 ADI A, 0xffff  ; 0x2134, 0xffff

[3][OR][MRD][r], addr        Example: LD  A, 0x03ff  ; 0x33a4, 0x03ff
[3][OR][r][MWR], addr                 STO A, 0x03ff  ; 0x334b, 0x03ff

[4][p][MRD][r]        Example: LDX  A, E   ; 0x48a4
[4][p][r][MWR]                 STOX A, E   ; 0x484b

Branches can be Unconditional or Conditional. They can also be Direct, Indirect, Relative or Relative Indirect.

Since "JP addr" is equivalent to: "MVI PC, addr", the unconditional jump instruction "JP addr" gets naturally encoded as a Class 2 instruction (Immediate transfers) as following:

[2][0][OR][PC], addr       0x2031  

For Conditional Branches, the condition is encoded in the OTA field as following:

[2][OTA][OR][PC], addr     Example: JNZ 0x03FF ; 0x2231, 0x03ff

OTA     Condition       Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       Zero            F0 = 1
2       Not Zero        F0 = 0
3       Negative        F1 = 1
4       Not Negative    F1 = 0
5       Carry           F2 = 1
6       Not Carry       F2 = 0
7       Overflow        F3 = 1
8       Not Overflow    F3 = 0
9       (Reserved)      F4 = 1
10      (Reserved)      F4 = 0
11      (Reserved)      F5 = 1
12      (Reserved)      F5 = 0
13      (Reserved)      F6 = 1
14      (Reserved)      F6 = 0
15      (Reserved)      F7 = 1

Note that the condition "OTA not equal to zero" could be confusing for the Class 2 decoding circuitry since it could either represents an immediate ALU instruction or a conditional branch. The circuit resolves the conflict by looking at the LD field: if LD=1 (PC) then it is a conditional branch instruction; otherwise it is an immediate ALU instruction.

Conditions 9-15 are "reserved" in the sense that no hardware circuit will set those flags for now. However, Class 2 instructions decoder circuitry is wired to cause actual jumps; for instance, the operational code "0x2a31, 0x3ff" will cause a jump to 0x3ff since F4 is zero after reset.

These are jump instructions using an indirect address provided by any of the general purpose registers B, C, D or E. Unconditional indirect jump instructions get naturally encoded as a Class 1 instructions:

[1][0][p][PC]                Example:  JPX   E    ;  0x1081

For conditional jumps, the jump condition is coded in the OTA field:

[1][condition][p][PC]        Example:  JNZX   E   ; 0x1281

The operand off-set, which is a signed 16-bits number, is added to the current PC content to cause a branch relative to the address of the current instruction. This will make easier for an Operating System to allocate programs anywhere in memory since they won't point to absolute memory addresses. Notice, however, that this off-set is limited to the range:    -32,768 to +32,767.

[5][0][OR][PC], off-set               Example: JPR   0x8   ; 0x5031, 0x0008
[5][condition][OR][PC], off-set       Example: JNZR  0x8   ; 0x5231, 0x0008  

Same as relative but using a general purpose register as a pointer (p).

[6][0][p][PC]               Example: JPRX   E   ; 0x6081
[6][condition][p][PC]       Example: JNZRX  E   ; 0x6281

Call instructions are special because they require more than four cycles to execute since PC and F need to be saved to the Stack before branching; however, these long sequences are built from the same ET0, ET1 signals provided by the "Time Counter" (T-Counter).

Call instructions are always unconditional. They can be Direct, Indirect, Relative or Relative Indirect.

The branch address is read into OR during the Fetch cycle.

[10][0][0R][PC], addr        Example: CALL  0x03ff   ; 0xa031, 0x03ff

[11][0][0R][PC], off-set        Example: CALLR  0x08   ; 0xb031, 0x08

These two addressing modes for CALL instructions are grouped together in Class 12 since they don't require an operand to be fetched. Field OTA indicates the addressing mode as following:

0: Indirect
1: Relative Indirect

The branch address is given by a general purpose register used as a pointer (p).

[12][0][p][PC]        Example: CALLX  d   ; 0xc071
[12][1][p][PC]                 CALLRX d   ; 0xc171

Stack operations Push and Pop takes separate classes (7 and 8 respectively) because of the
order in which operations are made. Field encoding is as following:

[7][SP][r][MWR]       Example: PUSH A     ; 0x724b
[8][SP][MRD][r]                POP  A     ; 0x82a4

Up to two registers can be incremented or decremented at the same time (in a single clock
cycle) by using the following instructions:

INC r           Increment register r
DEC r           Decrement register r
INCM  r1, r2    Increment registers r1 and r2 simultaneously
DECM  r1, r2    Decrement registers r1 and r2 simultaneously
INDEC r1, r2    Increment register r1 and decrement r2 simultaneously

All Increment/Decrement instructions are encoded the same way:

[9][mode][r2][r1]

The field [mode] determines what to do with registers r2, r1 according to the following table:

D11  D10  D9  D8                                     Example
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0    0    0    0    Do nothing                    
0    0    0    1    Increment r2                     INC   B
0    0    1    0    Decrement r2                     DEC   B
0    0    1    1    (Illegal)
0    1    0    0    Increment r1                     INC   A
0    1    0    1    Increment both r2 and r1         INCM  B, A
0    1    1    0    Increment r2 and Decrement r1    INDEC B, A
0    1    1    1    (Illegal)
1    0    0    0    Decrement r2                     DEC   B
1    0    0    1    Decrement r2 and Increment r1    INDEC A, B
1    0    1    0    Decrement both r2 and r1         DECM  B, A
1    0    1    1    (Illegal)
1    1    0    0    (Illegal)
1    1    0    1    (Illegal)
1    1    1    0    (Illegal)
1    1    1    1    (Illegal)