Table of Content  Branch Up  

The Lab implementation (2010)

This section describes the Heritage/1 Instructions Set Architecture in full details. A summarized list of all Heritage/1 instructions is also provided at the end of the section.

For all instructions in Heritage/1, the operational code takes a single 16-bits word. If an operand is needed, this is always the one 16-bit word following the Operational Code.

The Operational Code is divided into four 4-bits fields as shown below.

15                            0
[ CLASS ][ OTA  ][ OTD ][ LD  ]

The Instruction CLASS field (D12-15) determines how the other fields must be understood. It also determines whether the instruction requires an operand to be fetched and what actual circuit will decode the instruction.

For most instructions: OTA field (Output To Address) encodes the register providing the address, OTD (Output To Data) encodes the register used as source and LD field (Load) encodes the destination register. For memory read instructions, OTD = MRD (Memory Read signal); for memory write instructions, LD = MWR (Memory Write signal). Not used fields are filled with zeros.

Some instructions classes make special use of non-used fields as we shall see.

The following addressing modes have been implemented:

Register  : Data is contained in given register
            example: mov a, b      ; a=b

Immediate : Data if given in the word following the op. cod (operand).
            example: mvi  a, data  ;a=data

Direct    : Data is in the memory location which address is given in the word following the op. cod. (operand)
            example: ld a, addr    ; a=[addr]

Indirect  : Data is in the memory location which address is contained in a register used as a memory pointer
            example: ldx a, d      ; a=[d]

Relative  : (Branch only). Jump to OFF_SET relative to current instruction address. The OFF_SET if given as an operand.
            example: jnzr OFF_SET  ; pc=pc+OFF_SET

Relative Indirect: (Branch only). The OFF_SET is the content of given register.
           example: jnzrx  d      ; pc=pc+d

Stack     : Data comes from the Stack which is always pointed by register SP
            example:  pop a          ; sp=sp+1, a=[sp]

When a field represents a register, this is encoded according to the following table:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Value   Register         Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       PC               Program Counter
2       SP               Stack Pointer
3       OR               Operand Register
4       A                Accumulator
5       B                General Purpose reg
6       C                General Purpose reg
7       D                General Purpose reg
8       E                General Purpose reg
9-13   (reserved)        (Future use)
14      MRD              Memory Read signal              
15      MWR              Memory Write signal

For ALU instructions the OTA fields encode the ALU functions as following:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
OTA     Function       Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       ADD            Add
2       SUB            Subtract
3       CMP            Compare
4       AND            Logical AND  
5       OR             Logical OR
6       XOR            Logical XOR
7       SHFL           Shift Left
8       SHFR           Shift Right
9       SWP            Swap Nibbles
10-15   (Reserved)

Note:

All functions employ register A as left operand. The result is latched into A except for CMP which affects flags without altering A content.

As mentioned before, the Instruction CLASS determines how the other fields must be understood. It also determines whether the instruction requires an operand to be fetched and what actual circuit will decode the instruction.

Instructions classes are the following:

- - - - - - - - - - - - - - - - - - - - - -
Class  Description        Clock Cycles
- - - - - - - - - - - - - - - - - - - - - -
0      Null Class                  -
1      Register                    2
2      Immediate                   2
3      Direct                      3
4      Indirect                    3
5      Relative Direct             3
6      Relative Indirect           3
7      Stack Push                  4
8      Stack Pop                   4
9      Inc/Dec                     1
10     Call Direct                (more than 4)
11     Call Relative              (more than 4)
12     Call Relative Indirect     (more than 4)
13-14  (Future)                    -
15     Class Extensions            -

[1][0][r2][r1]        Example: MOV  A, B  ; 0x1045
[1][f][r ][A]                  ADD  A, B  ; 0x1145

[2][0][OR][r], value       Example:  MVI A, 0xffff  ; 0x2034, 0xffff
[2][f][OR][A], value                 ADI A, 0xffff  ; 0x2134, 0xffff

[3][OR][MRD][r], addr        Example: LD  A, 0x03ff  ; 0x33a4, 0x03ff
[3][OR][r][MWR], addr                 STO A, 0x03ff  ; 0x334b, 0x03ff

[4][p][MRD][r]        Example: LDX  A, E   ; 0x48a4
[4][p][r][MWR]                 STOX A, E   ; 0x484b

Branches can be Unconditional or Conditional. They can also be Direct, Indirect, Relative or Relative Indirect.

Since "JP addr" is equivalent to: "MVI PC, addr", the unconditional jump instruction "JP addr" gets naturally encoded as a Class 2 instruction (Immediate transfers) as following:

[2][0][OR][PC], addr       0x2031  

For Conditional Branches, the condition is encoded in the OTA field as following:

[2][OTA][OR][PC], addr     Example: JNZ 0x03FF ; 0x2231, 0x03ff

OTA     Condition       Remarks
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1       Zero            F0 = 1
2       Not Zero        F0 = 0
3       Negative        F1 = 1
4       Not Negative    F1 = 0
5       Carry           F2 = 1
6       Not Carry       F2 = 0
7       Overflow        F3 = 1
8       Not Overflow    F3 = 0
9       (Reserved)      F4 = 1
10      (Reserved)      F4 = 0
11      (Reserved)      F5 = 1
12      (Reserved)      F5 = 0
13      (Reserved)      F6 = 1
14      (Reserved)      F6 = 0
15      (Reserved)      F7 = 1

Note that the condition "OTA not equal to zero" could be confusing for the Class 2 decoding circuitry since it could either represents an immediate ALU instruction or a conditional branch. The circuit resolves the conflict by looking at the LD field: if LD=1 (PC) then it is a conditional branch instruction; otherwise it is an immediate ALU instruction.

Conditions 9-15 are "reserved" in the sense that no hardware circuit will set those flags for now. However, Class 2 instructions decoder circuitry is wired to cause actual jumps; for instance, the operational code "0x2a31, 0x3ff" will cause a jump to 0x3ff since F4 is zero after reset.

These are jump instructions using an indirect address provided by any of the general purpose registers B, C, D or E. Unconditional indirect jump instructions get naturally encoded as a Class 1 instructions:

[1][0][p][PC]                Example:  JPX   E    ;  0x1081

For conditional jumps, the jump condition is coded in the OTA field:

[1][condition][p][PC]        Example:  JNZX   E   ; 0x1281

The operand off-set, which is a signed 16-bits number, is added to the current PC content to cause a branch relative to the address of the current instruction. This will make easier for an Operating System to allocate programs anywhere in memory since they won't point to absolute memory addresses. Notice, however, that this off-set is limited to the range:    -32,768 to +32,767.

[5][0][OR][PC], off-set               Example: JPR   0x8   ; 0x5031, 0x0008
[5][condition][OR][PC], off-set       Example: JNZR  0x8   ; 0x5231, 0x0008  

Same as relative but using a general purpose register as a pointer (p).

[6][0][p][PC]               Example: JPRX   E   ; 0x6081
[6][condition][p][PC]       Example: JNZRX  E   ; 0x6281

Call instructions are special because they require more than four cycles to execute since PC and F need to be saved to the Stack before branching; however, these long sequences are built from the same ET0, ET1 signals provided by the "Time Counter" (T-Counter).

Call instructions are always unconditional. They can be Direct, Indirect, Relative or Relative Indirect.

The branch address is read into OR during the Fetch cycle.

[10][0][0R][PC], addr        Example: CALL  0x03ff   ; 0xa031, 0x03ff

[11][0][0R][PC], off-set        Example: CALLR  0x08   ; 0xb031, 0x08

These two addressing modes for CALL instructions are grouped together in Class 12 since they don't require an operand to be fetched. Field OTA indicates the addressing mode as following:

0: Indirect
1: Relative Indirect

The branch address is given by a general purpose register used as a pointer (p).

[12][0][p][PC]        Example: CALLX  d   ; 0xc071
[12][1][p][PC]                 CALLRX d   ; 0xc171

Stack operations Push and Pop takes separate classes (7 and 8 respectively) because of the
order in which operations are made. Field encoding is as following:

[7][SP][r][MWR]       Example: PUSH A     ; 0x724b
[8][SP][MRD][r]                POP  A     ; 0x82a4

Up to two registers can be incremented or decremented at the same time (in a single clock
cycle) by using the following instructions:

INC r           Increment register r
DEC r           Decrement register r
INCM  r1, r2    Increment registers r1 and r2 simultaneously
DECM  r1, r2    Decrement registers r1 and r2 simultaneously
INDEC r1, r2    Increment register r1 and decrement r2 simultaneously

All Increment/Decrement instructions are encoded the same way:

[9][mode][r2][r1]

The field [mode] determines what to do with registers r2, r1 according to the following table:

D11  D10  D9  D8                                     Example
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0    0    0    0    Do nothing                    
0    0    0    1    Increment r2                     INC   B
0    0    1    0    Decrement r2                     DEC   B
0    0    1    1    (Illegal)
0    1    0    0    Increment r1                     INC   A
0    1    0    1    Increment both r2 and r1         INCM  B, A
0    1    1    0    Increment r2 and Decrement r1    INDEC B, A
0    1    1    1    (Illegal)
1    0    0    0    Decrement r2                     DEC   B
1    0    0    1    Decrement r2 and Increment r1    INDEC A, B
1    0    1    0    Decrement both r2 and r1         DECM  B, A
1    0    1    1    (Illegal)
1    1    0    0    (Illegal)
1    1    0    1    (Illegal)
1    1    1    0    (Illegal)
1    1    1    1    (Illegal)

The value 15 in the Class field indicates a "Class Extension". Those are classes that don't
make use of fields OTA, OTD, LD. The circuitry to decode extended class instructions are in
IDS Extended cards.

Up to 15 class extensions can exists. They are indicated in the 4-bits field "Ext" (D9-11):

[15][Ext][arg]

The field "arg" is 8-bits. Its usage is determined by the Extension Class. At the time of writing, the following Class Extensions have been defined:

[15][1][vector]

(Vector is 8-bits)

Difference between RET and RETI is that the latest activates the ISE (Instruction Service End) control line in the External Bus as par of the negotiation with the interrupter peripheral (See Interrupt Architecture).

[15][2][0]         RET
[15][3][0]         RETI

Classes 13 and 14 are reserved for future use.